1.8 MM PITCH BGA Search Results

gs8182d18d200

Contextual Info: GS8182D18D-200/167 200 MHz–167 MHz 1.8 V VDD 1.8 V and 1.5 V I/O 18Mb Burst of 4 SigmaQuad-II SRAM 165-Bump BGA Commercial Temp Industrial Temp SigmaRAM Family Overview Bottom View 165-Bump, 13 mm x 15 mm BGA 1 mm Bump Pitch, 11 x 15 Bump Array JEDEC Std. MO-216, Variation CAB-1

Contextual Info: GS8182Q18/36D-200/167/133 200MHz–133MHz 1.8 V VDD 1.8 V and 1.5 V I/O 18Mb Burst of 2 SigmaQuad-II SRAM 165-Bump BGA Commercial Temp Industrial Temp SigmaRAM Family Overview Bottom View 165-Bump, 13 mm x 15 mm BGA 1 mm Bump Pitch, 11 x 15 Bump Array JEDEC Std. MO-216, Variation CAB-1

CYUSB301X

Contextual Info: CYUSB301X EZ-USB FX3 SuperSpeed USB Controller Features • Independent power domains for core and I/O ❐ Core operation at 1.2 V 2 ❐ I S, UART, and SPI operation at 1.8 to 3.3 V 2 ❐ I C operation at 1.2 V ■ 10- x 10-mm, 0.8-mm pitch Pb-free ball grid array BGA

Contextual Info: Preliminary GS8342D08/09/18/36E-400/300/250/200/167 36Mb SigmaQuad-II Burst of 4 SRAM 165-Bump BGA Commercial Temp Industrial Temp 167 MHz–400 MHz 1.8 V VDD 1.8 V and 1.5 V I/O Features • Simultaneous Read and Write SigmaQuad Interface • JEDEC-standard pinout and package

Contextual Info: Preliminary GS8662T08/09/18/36E-333/300/267*/250/200/167 72Mb SigmaCIO DDR-II Burst of 2 SRAM 165-Bump BGA Commercial Temp Industrial Temp 167 MHz–333 MHz 1.8 V VDD 1.8 V and 1.5 V I/O Features • Simultaneous Read and Write SigmaCIO Interface • Common I/O bus

GS818

Contextual Info: Preliminary GS8662S08/09/18/36E-333/300/250/200/167 167 MHz–333 MHz 1.8 V VDD 1.8 V and 1.5 V I/O 72Mb Burst of 2 DDR SigmaSIO-II SRAM 165-Bump BGA Commercial Temp Industrial Temp Features • Simultaneous Read and Write SigmaSIO Interface • JEDEC-standard pinout and package

Contextual Info: Preliminary GS8342Q08/09/18/36E-300/250/200/167 36Mb SigmaQuad-II Burst of 2 SRAM 165-Bump BGA Commercial Temp Industrial Temp 167 MHz–300 MHz 1.8 V VDD 1.8 V and 1.5 V I/O Features • Simultaneous Read and Write SigmaQuad Interface • JEDEC-standard pinout and package

k2333

Abstract: GS8342T GS8342T36
Contextual Info: Preliminary GS8342T08/18/36E-400/300/250/200/167 36Mb SigmaCIO DDR-II Burst of 2 SRAM 165-Bump BGA Commercial Temp Industrial Temp 167 MHz–400 MHz 1.8 V VDD 1.8 V and 1.5 V I/O Features • Simultaneous Read and Write SigmaCIO Interface • Common I/O bus

Contextual Info: Preliminary GS8662D08/09/18/36E-333/300/250/200/167 72Mb SigmaQuad-II Burst of 4 SRAM 165-Bump BGA Commercial Temp Industrial Temp 167 MHz–333 MHz 1.8 V VDD 1.8 V and 1.5 V I/O Features • Simultaneous Read and Write SigmaQuad Interface • JEDEC-standard pinout and package

Contextual Info: Preliminary GS8662R08/09/18/36E-333/300/250/200/167 72Mb SigmaCIO DDR-II Burst of 4 SRAM 165-Bump BGA Commercial Temp Industrial Temp 167 MHz–333 MHz 1.8 V VDD 1.8 V and 1.5 V I/O Features • Simultaneous Read and Write SigmaCIO Interface • Common I/O bus

ECHO schematic diagrams

Contextual Info: Preliminary GS8170LW18/36/72C-333/300/250 18Mb Σ1x1 Late Write SigmaRAM SRAM 209-Bump BGA Commercial Temp Industrial Temp 250 MHz–333 MHz 1.8 V VDD 1.8 V and 1.5 V I/O Features • Late Write mode • Pipeline read operation • JEDEC-standard SigmaRAM™ pinout and package

Contextual Info: Preliminary GS8342Q08/09/18/36E-300/250/200/167 36Mb SigmaQuad-II Burst of 2 SRAM 165-Bump BGA Commercial Temp Industrial Temp 167 MHz–300 MHz 1.8 V VDD 1.8 V and 1.5 V I/O Features • Simultaneous Read and Write SigmaQuad Interface • JEDEC-standard pinout and package

GS8180D18D-100

Abstract: GS8180D18D-133 GS8180D18D-167 GS8180D18D-167I GS8180D18D-200 GS8180D18D-200I GS8180D18D-250 GS8180D18D-250I
Contextual Info: GS8180D18D-250/200/167/133/100 250 MHz–100 MHz 1.8 V VDD 1.8 V or 1.5 V I/O 18Mb Burst of 4 SigmaQuad SRAM 165-Bump BGA Commercial Temp Industrial Temp Features • Simultaneous Read and Write SigmaQuad Interface • JEDEC-standard pinout and package

Contextual Info: Preliminary GS8342S08/18/36E-400/300/250/200/167 36Mb Burst of 2 DDR SigmaSIO-II SRAM 165-Bump BGA Commercial Temp Industrial Temp 167 MHz–400 MHz 1.8 V VDD 1.8 V and 1.5 V I/O Features • Simultaneous Read and Write SigmaSIO Interface • JEDEC-standard pinout and package

Contextual Info: Preliminary GS8342D08/18/36E-400/300/250/200/167 36Mb SigmaQuad-II Burst of 4 SRAM 165-Bump BGA Commercial Temp Industrial Temp 167 MHz–400 MHz 1.8 V VDD 1.8 V and 1.5 V I/O Features • Simultaneous Read and Write SigmaQuad Interface • JEDEC-standard pinout and package

Contextual Info: Preliminary GS8342R08/18/36E-400/300/250/200/167 36Mb SigmaCIO DDR-II Burst of 4 SRAM 165-Bump BGA Commercial Temp Industrial Temp 167 MHz–400 MHz 1.8 V VDD 1.8 V and 1.5 V I/O Features • Simultaneous Read and Write SigmaCIO Interface • Common I/O bus

Contextual Info: Preliminary GS8182S18/36D-330/300/250/200/167/133 18Mb Σ2x1B2 DDR SigmaSIO-II SRAM 165-Bump BGA Commercial Temp Industrial Temp 133 MHz–330 MHz 1.8 V VDD 1.8 V and 1.5 V I/O Features • Simultaneous Read and Write SigmaQuad Interface • JEDEC-standard pinout and package

ECHO schematic diagrams

Abstract: 8170D18 8170D36 GS8170D36B-300 GS8170D36B-333 Sigma ddr
Contextual Info: Advanced Information GS8170D18/36B-333/300/275/250 209-Bump BGA Commercial Temp Industrial Temp ΣRAM 1M x 18, 512K x 36 16Mb DDR SRAM 333 MHz 1.8 V VDD 1.8 V and 1.5 V I/O Features • Double Data Rate Read and Write mode • Observes the Sigma RAM pinout standard

MCL 1 029

Abstract: ECHO schematic diagrams 2000-23 k4 8180S18 8180S36 GS8180S36B-333 Sigma ddr
Contextual Info: Advanced Information GS8180S09/18/36B-333/300/275/250 209-Bump BGA Commercial Temp Industrial Temp ΣRAM 2M x 9, 1M x 18, 512K x 36 Separate I/O Sigma SDR SRAM 333 MHz 1.8 V VDD 1.8 V and 1.5 V I/ Features • Observes the Sigma RAM pinout standard • 1.8 V +150/–100 mV core power supply

ECHO schematic diagrams

Abstract: flip chip bga 0,8 mm
Contextual Info: Preliminary GS8170DW18/36/72C-333/300/250 18Mb Σ1x1 Double Late Write SigmaRAM SRAM 209-Bump BGA Commercial Temp Industrial Temp 250 MHz–333 MHz 1.8 V VDD 1.8 V and 1.5 V I/O Features • Double Late Write mode • JEDEC-standard SigmaRAM™ pinout and package

GS8182S36D-167

Abstract: GS8182S36D-200 GS8182S36D-250 GS8182S36D-300 GS8182S36D-333I
Contextual Info: Preliminary GS8182S18/36D-333/300/250/200/167 18Mb Burst of 2 DDR SigmaSIO-II SRAM 165-Bump BGA Commercial Temp Industrial Temp 167 MHz–333 MHz 1.8 V VDD 1.8 V and 1.5 V I/O Features • Simultaneous Read and Write SigmaQuad Interface • JEDEC-standard pinout and package

8170S18

Abstract: 8170S36 8170S72
Contextual Info: Advanced Information GS8170S18/36/72B-333/300/275/250 209-Bump BGA Commercial Temp Industrial Temp 1M x 18, 512K x 36, 256K x 72 RAM Σ 16Mb Synchronous SRAM 333 MHz 1.8 V VDD 1.8 V and 1.5 V I/O Features • User-configurable Early, Late, and Double Late Write modes

Contextual Info: Preliminary GS8182S18/36D-333/300/250/200/167 18Mb Σ2x1B2 DDR SigmaSIO-II SRAM 165-Bump BGA Commercial Temp Industrial Temp 167 MHz–333 MHz 1.8 V VDD 1.8 V and 1.5 V I/O Features • Simultaneous Read and Write SigmaQuad Interface • JEDEC-standard pinout and package

GS8182S36D-200

Abstract: GS8182S36D-250 GS8182S36D-300
Contextual Info: Preliminary GS8182S18/36D-333/300/250/200/167 18Mb Σ2x1B2 DDR SigmaSIO-II SRAM 165-Bump BGA Commercial Temp Industrial Temp 167 MHz–333 MHz 1.8 V VDD 1.8 V and 1.5 V I/O Features • Simultaneous Read and Write SigmaQuad Interface • JEDEC-standard pinout and package