8170LW18 Search Results

GS8170DW36C-200

Abstract: GS8170DW36C-250 GS8170DW36C-300 GS8170DW36C-333
Contextual Info: Preliminary GS8170DW36/72C-333/300/250/200 18Mb Σ1x1Dp CMOS I/O 209-Bump BGA Commercial Temp Industrial Temp 200 MHz–333 MHz 1.8 V VDD 1.8 V I/O Double Late Write SigmaRAM Features • Double Late Write mode, Pipelined Read mode • JEDEC-standard SigmaRAM™ pinout and package

Contextual Info: GS8170LW36/72C-333/300/250/200 209-Bump BGA Commercial Temp Industrial Temp 18Mb Σ1x1Lp CMOS I/O Late Write SigmaRAM 200 MHz–333 MHz 1.8 V VDD 1.8 V I/O Features • Late Write mode, Pipelined Read mode • JEDEC-standard SigmaRAM™ pinout and package

ECHO schematic diagrams

Contextual Info: Preliminary 8170LW18/36/72C-333/300/250 18Mb Σ1x1 Late Write SigmaRAM SRAM 209-Bump BGA Commercial Temp Industrial Temp 250 MHz–333 MHz 1.8 V VDD 1.8 V and 1.5 V I/O Features • Late Write mode • Pipeline read operation • JEDEC-standard SigmaRAM™ pinout and package

72C33

Abstract: DSA00180016.txt
Contextual Info: Preliminary 8170LW18/36/72C-333/300/250 18Mb Σ1x1 Late Write SigmaRAM SRAM 209-Bump BGA Commercial Temp Industrial Temp 250 MHz–333 MHz 1.8 V VDD 1.8 V and 1.5 V I/O Features • Late Write mode • User-configurable pipeline and flow through operation

Contextual Info: Preliminary GS8170LW36/72C-333/300/250/200 18Mb Σ1x1Lp CMOS I/O 209-Bump BGA Commercial Temp Industrial Temp 200 MHz–333 MHz 1.8 V VDD 1.8 V I/O Late Write SigmaRAM Features • Late Write mode, Pipelined Read mode • JEDEC-standard SigmaRAM™ pinout and package

GS8170LW72C-250

Abstract: GS8170LW72C-300 GS8170LW72C-333 GS8170LW72C-333I
Contextual Info: GS8170LW36/72C-333/300/250/200 209-Bump BGA Commercial Temp Industrial Temp 18Mb Σ1x1Lp CMOS I/O Late Write SigmaRAM Features 200 MHz–333 MHz 1.8 V VDD 1.8 V I/O Functional Description • Late Write mode, Pipelined Read mode • JEDEC-standard SigmaRAM™ pinout and package