GS8662TXX Search Results

Contextual Info: GS8662T08/09/18/36E-333/300/250/200/167 72Mb SigmaDDR-II Burst of 2 SRAM • Simultaneous Read and Write SigmaDDR-II™ Interface • Common I/O bus • JEDEC-standard pinout and package • Double Data Rate interface • Byte Write x36 and x18 and Nybble Write (x8) function

Contextual Info: GS8662T07/10/19/37BD-450/400/350/333/300 72Mb SigmaDDR-II+TM Burst of 2 SRAM 165-Bump BGA Commercial Temp Industrial Temp 450 MHz–300 MHz 1.8 V VDD 1.8 V or 1.5 V I/O Features • 2.0 Clock Latency • Simultaneous Read and Write SigmaDDR Interface • Common I/O bus

Contextual Info: GS8662T08/09/18/36E-333/300/250/200/167 72Mb SigmaCIO DDR-II Burst of 2 SRAM 165-Bump BGA Commercial Temp Industrial Temp 333 MHz–167 MHz 1.8 V VDD 1.8 V and 1.5 V I/O Features • Simultaneous Read and Write SigmaCIO Interface • Common I/O bus • JEDEC-standard pinout and package

Contextual Info: GS8662T19/37AE-400/375/333/300 72Mb SigmaCIO DDR-II+ Burst of 2 SRAM 165-Bump BGA Commercial Temp Industrial Temp 400 MHz–300 MHz 1.8 V VDD 1.8 V and 1.5 V I/O Features • 2.0 Clock Latency • Simultaneous Read and Write SigmaCIO Interface • Common I/O bus

Contextual Info: GS8662T08/09/18/36E-333/300/250/200/167 72Mb SigmaDDR-II Burst of 2 SRAM 165-Bump BGA Commercial Temp Industrial Temp Features • Simultaneous Read and Write SigmaDDR-II™ Interface • Common I/O bus • JEDEC-standard pinout and package • Double Data Rate interface

Contextual Info: GS8662T08/09/18/36BD-400/350/333/300/250 72Mb SigmaDDR-IITM Burst of 2 SRAM 165-Bump BGA Commercial Temp Industrial Temp 400 MHz–250 MHz 1.8 V VDD 1.8 V and 1.5 V I/O Features • Simultaneous Read and Write SigmaDDR Interface • Common I/O bus • JEDEC-standard pinout and package

Contextual Info: Preliminary GS8662T08/09/18/36E-333/300/267/250/200/167 72Mb SigmaCIO DDR-II Burst of 2 SRAM 165-Bump BGA Commercial Temp Industrial Temp 333 MHz–167 MHz 1.8 V VDD 1.8 V and 1.5 V I/O Features • Simultaneous Read and Write SigmaCIO Interface • Common I/O bus

mhz300

Contextual Info: GS8662T07/10/19/37BD-450/400/350/333/300 72Mb SigmaDDR-II+TM Burst of 2 SRAM 165-Bump BGA Commercial Temp Industrial Temp 450 MHz–300 MHz 1.8 V VDD 1.8 V or 1.5 V I/O Features • 2.0 Clock Latency • Simultaneous Read and Write SigmaDDR Interface • Common I/O bus

Contextual Info: GS8662T07/10/19/37BD-450/400/350/333/300 72Mb SigmaDDR-II+TM Burst of 2 SRAM 165-Bump BGA Commercial Temp Industrial Temp Features • 2.0 Clock Latency • Simultaneous Read and Write SigmaDDR Interface • Common I/O bus • JEDEC-standard pinout and package

Contextual Info: Preliminary GS8662T08/09/18/36E-333/300/267*/250/200/167 72Mb SigmaCIO DDR-II Burst of 2 SRAM 165-Bump BGA Commercial Temp Industrial Temp 167 MHz–333 MHz 1.8 V VDD 1.8 V and 1.5 V I/O Features • Simultaneous Read and Write SigmaCIO Interface • Common I/O bus

Contextual Info: Preliminary GS8662T07/10/19/37BD-450/400/375/333 72Mb SigmaDDR-II+TM Burst of 2 SRAM 165-Bump BGA Commercial Temp Industrial Temp 450 MHz–333 MHz 1.8 V VDD 1.8 V or 1.5 V I/O Features • 2.0 Clock Latency • Simultaneous Read and Write SigmaDDR Interface

Contextual Info: GS8662T08/09/18/36BD-400/350/333/300/250 72Mb SigmaDDR-IITM Burst of 2 SRAM 165-Bump BGA Commercial Temp Industrial Temp Features • Simultaneous Read and Write SigmaDDR Interface • Common I/O bus • JEDEC-standard pinout and package • Double Data Rate interface

Contextual Info: GS8662T08/09/18/36E-250/200/167 72Mb SigmaDDR-II Burst of 2 SRAM • Simultaneous Read and Write SigmaDDR-II™ Interface • Common I/O bus • JEDEC-standard pinout and package • Double Data Rate interface • Byte Write x36 and x18 and Nybble Write (x8) function

AN1019

Contextual Info: AN1019 SigmaQuad-II+ and SigmaDDR-II+ On-Die Termination ODT Introduction When an electrical signal is transmitted along a transmission line, it is reflected back when it reaches the end of the line. That reflection induces noise which adversely affects the quality of the signal, thereby making it more difficult for the receiving device

Contextual Info: Preliminary GS8662T08/09/18/36E-333/300/267/250/200/167 72Mb SigmaCIO DDR-II Burst of 2 SRAM 165-Bump BGA Commercial Temp Industrial Temp 333 MHz–167 MHz 1.8 V VDD 1.8 V and 1.5 V I/O Features • Simultaneous Read and Write SigmaCIO Interface • Common I/O bus

Contextual Info: GS8662T08/09/18/36BD-350M 165-Bump BGA Military Temp 72Mb SigmaDDR-IITM Burst of 2 SRAM Features • Military Temperature Range • Simultaneous Read and Write SigmaDDR Interface • Common I/O bus • JEDEC-standard pinout and package • Double Data Rate interface

Contextual Info: GS8662T07/10/19/37BD-450/400/350/333/300 72Mb SigmaDDR-II+TM Burst of 2 SRAM 165-Bump BGA Commercial Temp Industrial Temp Features • 2.0 Clock Latency • Simultaneous Read and Write SigmaDDR Interface • Common I/O bus • JEDEC-standard pinout and package

GS8662T18BD

Contextual Info: GS8662T08/09/18/36BD-400/350/333/300/250 72Mb SigmaDDR-IITM Burst of 2 SRAM 165-Bump BGA Commercial Temp Industrial Temp Features • Simultaneous Read and Write SigmaDDR Interface • Common I/O bus • JEDEC-standard pinout and package • Double Data Rate interface

Contextual Info: GS8662T08/09/18/36BD-400/350/333/300/250 72Mb SigmaDDR-IITM Burst of 2 SRAM 165-Bump BGA Commercial Temp Industrial Temp Features • Simultaneous Read and Write SigmaDDR Interface • Common I/O bus • JEDEC-standard pinout and package • Double Data Rate interface

Contextual Info: Preliminary GS8662T07/10/19/37BD-450/400/350/333/300 72Mb SigmaDDR-II+TM Burst of 2 SRAM 165-Bump BGA Commercial Temp Industrial Temp 450 MHz–300 MHz 1.8 V VDD 1.8 V or 1.5 V I/O Features • 2.0 Clock Latency • Simultaneous Read and Write SigmaDDR Interface

GS8662T18BD-250

Abstract: GS8662T18BGD-250
Contextual Info: Preliminary GS8662T08/09/18/36BD-400/350/333/300/250 72Mb SigmaDDR-IITM Burst of 2 SRAM 165-Bump BGA Commercial Temp Industrial Temp 400 MHz–250 MHz 1.8 V VDD 1.8 V and 1.5 V I/O Features • Simultaneous Read and Write SigmaDDR Interface • Common I/O bus

Contextual Info: GS8662T08/09/18/36E-333/300/250/200/167 72Mb SigmaCIO DDR-II Burst of 2 SRAM 165-Bump BGA Commercial Temp Industrial Temp 333 MHz–167 MHz 1.8 V VDD 1.8 V and 1.5 V I/O Features • Simultaneous Read and Write SigmaCIO Interface • Common I/O bus • JEDEC-standard pinout and package

Contextual Info: Preliminary GS8662T08/09/18/36E-333/300/267*/250/200/167 72Mb SigmaCIO DDR-II Burst of 2 SRAM 165-Bump BGA Commercial Temp Industrial Temp 333 MHz–167 MHz 1.8 V VDD 1.8 V and 1.5 V I/O Features • Simultaneous Read and Write SigmaCIO Interface • Common I/O bus

Contextual Info: Preliminary GS8662T20/38AE-450/400/375/333/300 72Mb SigmaCIO DDR-II+ Burst of 2 SRAM 165-Bump BGA Commercial Temp Industrial Temp 450 MHz–300 MHz 1.8 V VDD 1.8 V and 1.5 V I/O Features • 2.5 Clock Latency • Simultaneous Read and Write SigmaCIO Interface