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    LH521002 Price and Stock

    Sharp Microelectronics of the Americas LH521002AK-35

    Distributors Part Package Stock Lead Time Min Order Qty Price Buy
    Bristol Electronics LH521002AK-35 11 2
    • 1 -
    • 10 $2.912
    • 100 $2.912
    • 1000 $2.912
    • 10000 $2.912
    		Buy Now
    Quest Components LH521002AK-35 8
    • 1 $6
    • 10 $3
    • 100 $3
    • 1000 $3
    • 10000 $3
    		Buy Now

    Sharp Microelectronics of the Americas LH521002AK-20

    IC,SRAM,256KX4,CMOS,SOJ,28PIN,PLASTIC
    Distributors Part Package Stock Lead Time Min Order Qty Price Buy
    Quest Components LH521002AK-20 4,113
    • 1 $7.5
    • 10 $7.5
    • 100 $7.5
    • 1000 $2.75
    • 10000 $2.625
    		Buy Now

    Sharp Microelectronics of the Americas LH521002AK-25

    256K X 4 STANDARD SRAM, 25 ns, PDSO28
    Distributors Part Package Stock Lead Time Min Order Qty Price Buy
    Quest Components LH521002AK-25 1,648
    • 1 $12.75
    • 10 $12.75
    • 100 $12.75
    • 1000 $4.4625
    • 10000 $4.4625
    		Buy Now

    Sharp Microelectronics of the Americas LH521002K-25

    256K X 4 STANDARD SRAM, 25 NS, PDSO28
    Distributors Part Package Stock Lead Time Min Order Qty Price Buy
    Quest Components LH521002K-25 100
    • 1 $9
    • 10 $4.5
    • 100 $3.9
    • 1000 $3.9
    • 10000 $3.9
    		Buy Now
    LH521002K-25 4
    • 1 $20.6642
    • 10 $18.3682
    • 100 $18.3682
    • 1000 $18.3682
    • 10000 $18.3682
    		Buy Now

    Sharp Microelectronics of the Americas LH521002BK-20

    521002BK-20
    Distributors Part Package Stock Lead Time Min Order Qty Price Buy
    Quest Components LH521002BK-20 32
    • 1 $5.25
    • 10 $2.625
    • 100 $2.625
    • 1000 $2.625
    • 10000 $2.625
    		Buy Now
    Find more LH521002 price and stock on Findchips.com

    LH521002 Datasheets (30)

    Part ECAD Model Manufacturer Description Curated Datasheet Type PDF
    LH521002AK-17 Sharp SRAM GP Single Port Original PDF
    LH521002AK-20 Sharp SRAM GP Single Port Original PDF
    LH521002AK-25 Sharp SRAM GP Single Port Original PDF
    LH521002BK-17 Sharp SRAM GP Single Port Original PDF
    LH521002BK-17L Sharp SRAM GP Single Port Original PDF
    LH521002BK-20 Sharp SRAM GP Single Port Original PDF
    LH521002BK-20L Sharp SRAM GP Single Port Original PDF
    LH521002BK-25 Sharp SRAM GP Single Port Original PDF
    LH521002BK-25L Sharp SRAM GP Single Port Original PDF
    LH521002BK-35 Sharp SRAM GP Single Port Original PDF
    LH521002BK-35L Sharp SRAM GP Single Port Original PDF
    LH521002BNK-17 Sharp SRAM GP Single Port Original PDF
    LH521002BNK-17L Sharp SRAM GP Single Port Original PDF
    LH521002BNK-20 Sharp SRAM GP Single Port Original PDF
    LH521002BNK-20L Sharp SRAM GP Single Port Original PDF
    LH521002BNK-25 Sharp SRAM GP Single Port Original PDF
    LH521002BNK-25L Sharp SRAM GP Single Port Original PDF
    LH521002BNK-35 Sharp SRAM GP Single Port Original PDF
    LH521002BNK-35L Sharp SRAM GP Single Port Original PDF
    LH521002CK-17 Sharp SRAM GP Single Port Original PDF

    LH521002 Datasheets Context Search

    Catalog Datasheet MFG & Type PDF Document Tags

    LH521002AK25

    Abstract: No abstract text available
    Text: LH521002A CMOS 256K x 4 Static RAM • Low Power Standby when Deselected High frequency design techniques should be employed to obtain the best performance from this device. Solid, low impedance power and ground planes, with high frequency decoupling capacitors, are desirable. Series


    Original     		PDF LH521002A LH521002A 28SOJ SOJ28-P-400) 28SOJ400 28-pin, 400-mil LH521002AK25

    SOJ28-P-400

    Abstract: No abstract text available
    Text: LH521002C CMOS 256K x 4 Static RAM Data Sheet The ‘L’ version will retain data down to a supply voltage of 2 V. A significantly lower current can be obtained IDR under this Data Retention condition. CMOS Standby Current (ISB2) is reduced on the ‘L’ version with respect to


    Original     		PDF LH521002C 2613-banchi, J63428 SMT94020 SOJ28-P-400

    32-PIN

    Abstract: No abstract text available
    Text: LH521002B FEATURES • Fast Access Times: 17/20/25/35 ns • JEDEC Standard Pinouts • Low Power Standby when Deselected • TTL Compatible I/O • 5 V ± 10% Supply • Fully Static Operation • 2 V Data Retention L Version • Packages: 28-pin, 300-mil SOJ (Preliminary)


    Original     		PDF LH521002B 28-pin, 300-mil 400-mil 28SOJ400 32-PIN

    km681001j-20

    Abstract: TC55B328J-12 256Kx4 TC55B465J10 TC55B8128J20 PDM41028SA-15SO TC55B8128J-12 TC55328J-20 KM681001J-25 PDM41024S20
    Text: Cross Reference Guide Cross Reference Guide ALLIANCE VS PARADIGM AS7C1024-10TJ AS7C1024-12TJ AS7C1024-15TJ AS7C1024-20TJ AS7C1024L-10TJ AS7C1024L-12TJ AS7C1024L-15TJ AS7C1024L-20TJ AS7C1028-10TJ AS7C1028-12TJ AS7C1028-15TJ AS7C1028-20TJ AS7C1028L-10TJ AS7C1028L-12TJ


    Original     		PDF AS7C1024-10TJ AS7C1024-12TJ AS7C1024-15TJ AS7C1024-20TJ AS7C1024L-10TJ AS7C1024L-12TJ AS7C1024L-15TJ AS7C1024L-20TJ AS7C1028-10TJ AS7C1028-12TJ km681001j-20 TC55B328J-12 256Kx4 TC55B465J10 TC55B8128J20 PDM41028SA-15SO TC55B8128J-12 TC55328J-20 KM681001J-25 PDM41024S20

    Untitled

    Abstract: No abstract text available
    Text: LH521002A CMOS 256K x 4 Static RAM • Low Power Standby when Deselected High frequency design techniques should be em­ ployed to obtain the best performance from this device. Solid, low impedance power and ground planes, with high frequency decoupling capacitors, are desirable. Series


    OCR Scan     		PDF LH521002A 28-pin, 400-mil 28SOJ SOJ28-P-400) LH521002A ---------------------------------28-pin,

    Untitled

    Abstract: No abstract text available
    Text: LH521002C SHARP CMOS 256K x 4 Static RAM Data Sheet FEATURES The ‘L’ version will retain data down to a supply voltage of 2 V. A significantly lower current can be obtained Idr under this Data Retention condition. CMOS Standby Current (lSB2) ¡s reduced on the ‘L’ version with respect to


    OCR Scan     		PDF 28-pin, 300-mil 400-mil LH521002C 28SOJ400 LH521 28-Din.

    Untitled

    Abstract: No abstract text available
    Text: SHARP CORP blE D • filflDTTfi OOO^flfi Mbb * S R P J LH521002 FEATURES • Fast Access Times: 20/25/35 ns • JEDEC Standard Pinouts • Low Power Standby when Deselected • TTL Compatible I/O • 5 V ± 10% Supply • Fully Static Operation • Common I/O for Low Pin Count


    OCR Scan     		PDF LH521002 28-Pin, 400-mil SOJ28-P-4QO) LH521002K-25

    S21002

    Abstract: No abstract text available
    Text: LH521002 FEATURES • Fast Access Times: 20 725/35 ns • High Density 28-Pin, 400-mil SOJ • JEDEC Standard Pinouts • Low Power Standby when Deselected • TTL Compatible I/O • 5 V± 10% Supply • Fully Static Operation • Common I/O for Low Pin Count


    OCR Scan     		PDF LH521002 28-Pin, 400-mil SOJ28-P-400) LH521002K-25 S21002M S21002

    Untitled

    Abstract: No abstract text available
    Text: SHARP LH521002C CMOS 256K x 4 Static RAM Data Sheet The ‘L’ version will retain data down to a supply voltage of 2 V. A significantly lower current can be obtained Idr under this Data Retention condition. CMOS Standby Current (lSB2) is reduced on the ‘L’ version with respect to


    OCR Scan     		PDF LH521002C 28-pin, 300-mil 400-mil 300-MILSOJ 28SOJ SOJ28-P-4QO)

    lh57257

    Abstract: IR2E31 IR2E01 IR2C07 IR2E27 IR2E24 IR2E19 IR2E31A IR3n06 IR2E02
    Text: Index Model No. ARM7D CPU Core Bi-CMOS 1 27 40,42 _ _ CMOS CMOS CMOS CMOS CMOS 4A 5A 8 A AH D ID1 Series ID2 Series 40,42 40.42 40,42 40,42 40 B ü.’1*"! 14,15 14 m IR2339 IR2403 IR2406 IR2406G IR2410 IR2411 IR2415 IR2419 IR2420 IR2422 IR2425 IR2429


    OCR Scan     		PDF IR2E201 IR2E24 IR2E27/A IR2E28 IR2E29 IR2E30 IR2E31/A IR2E32N9 IR2E34 IR2E41 lh57257 IR2E31 IR2E01 IR2C07 IR2E27 IR2E19 IR2E31A IR3n06 IR2E02

    Untitled

    Abstract: No abstract text available
    Text: MEMORIES * S tic RAMs Process C apacity Configuration Model No. A ccess tim e ns 70 80 90 100 120 LH5116 16k Full CMOS 64k 2k X 8 8k X 8 LH5116H f- Supply voltage : 5 V * 10% QpewBng tew ^raw » : ~ 40to85'C LH5116S j- Supply voltage : 3 V ± 10% LH5164A


    OCR Scan     		PDF LH5116 LH5116H LH5116S LH5164A LH5164AH 40to85 LH5164AV LH51V256H LH5268A LH52256A

    BNK-17

    Abstract: No abstract text available
    Text: MEMORIES ★Under development • S ta tic RA M s Process Capacity Configuration words X bits Modal No. 2k X 8 Full CMOS 64k 8k X 8 256k 32k X 8 64k 8k X 8 64k X 4 256k 32k X 8 64k X 8 CMOS periphery 100 40/0.001 5 ± 10% O to 70 100 40/0.001 5 ± 10% - 4 0 to 85


    OCR Scan     		PDF LH5116/NA/D-10 LH5116H/HN/HD-10 LH5116SN 24SOP 28SOJ 400mil) LH521002BK/BNK-17/L LH521002BK/BNK-20/L LH521002BK/BNK-2S/L LH521007AK-20 BNK-17

    Untitled

    Abstract: No abstract text available
    Text: CMOS 256K x 4 Static RAM FEATURES • Fast Access Times: 20/25/35 ns • JEDEC Standard Pinouts Read cycles occur when E is LOW and W is HIGH. A Read cycle will^begin upon an addressjransition, on a falling edge of E, or on a rising edge of W. • 5 V ±10% Supply


    OCR Scan     		PDF 28-PIN 28-Pin, 400-mil LH521002 SOJ28-P-400) LH521002K-25 521002MO

    LH5160N

    Abstract: LH5115 LH5118D LH5160 LH5160D LH521000 LH5167 LH52252A LH5114H LH5911-55
    Text: NOV 0 5 1990 L H 5 9 1 1 /L H 5 9 1 2 /L H 5 9 1 4 2K x 8 CMOS Dual Port RAM Preliminary Data Sheet Features Functional Description The IH 5911, LH5912 and LH5914are dual port static RAMs that use true dual port memory cells to allow each port to independently access any location in memory.


    OCR Scan     		PDF LH5912 LH5914are LH5911 LH5914 /IDT7134 16Kx18 64Kx18 LH5160N LH5115 LH5118D LH5160 LH5160D LH521000 LH5167 LH52252A LH5114H LH5911-55

    organizational structure samsung

    Abstract: NMS256X8 MICRON Cross Reference NMS256 256K RAM HM62256 MK6264 51256SL TC5565 "cross reference" MN44256 M5M5256
    Text: Static RAM Cross Reference STATIC RAM CROSS REFERENCE ORGANIZATIONAL STRUCTURE 2K 2K X X 32K 8K X e w/CE, OE 8 W/CE1, CE2 X 8 Stow 8 Slow COMPETITIVE VENDOR SH ARP MODEL LH5116 LH5118 LH51256 LH5164A AMD Am9128 Harris CDM6116 Hitachi HM6116A Hyundai HY6116


    OCR Scan     		PDF LH5116 Am9128 CDM6116 HM6116A HY6116 HM6116 MS6516 SRM2016 MK6116 CXK5816 organizational structure samsung NMS256X8 MICRON Cross Reference NMS256 256K RAM HM62256 MK6264 51256SL TC5565 "cross reference" MN44256 M5M5256

    521002

    Abstract: lh521002
    Text: C M O S 256K x 4 Static RAM FEATURES • Fast Access Times: 20/25/35 ns • Low Power Standby when Deselected • TTL Compatible I/O • 5 V ± 10% Supply • Fully Static Operation • Common I/O for Low Pin Count • 2 V Data Retention • JEDEC Standard Pinouts


    OCR Scan     		PDF 28-Pin, 400-mil LH521002 LH521002 SOJ28-P-4 LH521002K-25 521002MD 521002

    LH5911

    Abstract: lh5167-55 LH5101 LH52250 LH5160D LH5167 LH52252 LH5114H lh5160n 4kx8 static ram ttl
    Text: NOV 0 5 1990 L H 5 9 1 1 /L H 5 9 1 2 /L H 5 9 1 4 2K x 8 CMOS Dual Port RAM Preliminary Data Sheet Functional Description Features The LH5911. LH5912 and LH5914are dual port static RAMs that use true dual port memory cells to allow each port to independently access any location in memory.


    OCR Scan     		PDF LH5911 /LH5912/LH5914 LH5911. LH5912 LH5914are LH5914 16Kx18 LH52270 lh5167-55 LH5101 LH52250 LH5160D LH5167 LH52252 LH5114H lh5160n 4kx8 static ram ttl

    lh5168

    Abstract: No abstract text available
    Text: MEMORIES Static RAMs ★ Under development P ro ce ss C a p a c ity C o n fig u ra tio n Model No. A c c e s s tim e n s 70 80 90 100 120 LH5116 2k X 8 16k LH51116H Operating temperature : - 40 to 8 5 t IUUU "O LH5116S Supply voltage : 3 V±10% LH5168 Full


    OCR Scan     		PDF LH5116 LH51116H LH5116S LH5168 LH5168H LH5168V LH5168S LH5168SH LH5164AH 5164AV

    5268A

    Abstract: 28-SOP LH521002AK-2S 28SOP LH52256CVN
    Text: MEMORIES S tatic RAMs Process Capacity Configuation words Xbits 2k 16k 8 X Access time Supply current ns) MAX. Cycle time Operating, Standby (ns) MIN. !mA) MAX. (mA) MAX. Model No. Supply Operating voltage temp. 0C) m i i LH 5116/NA/D-10 100 40 0.001 5 ± 10%


    OCR Scan     		PDF 5116/NA/D-10 LH5116H/HN/HD-10 LH5116SN LH5164A/AN-80L LH5164A /AT-10L 24DIP/24SOP/24SK-DIP 24SOP 28SOP/ 5268A 28-SOP LH521002AK-2S 28SOP LH52256CVN

    Spil polyimide system in package

    Abstract: B-629
    Text: SHARP LH521007C Data Sheet CMOS 128K X 8 Static RAM FEATURES When both Chip Enables are active and W is inactive, a static Read will occur at the memory location specified by the address lines. G must be brought LOW to enable the outputs. Since the device is fully static in operation,


    OCR Scan     		PDF 32-Pin, 300-mil 400-mil LH521007C 576-bit -65sC~ 2604C 1500G, LH521002CK Spil polyimide system in package B-629

    9660t

    Abstract: LH521008
    Text: SHARP b OE CORP D • Ô1ÔD7TÔ DDDTME? 302 «SRPJ 'T - H C - 2 3 - / O LH101504 LH101510 . R E L I M I N A Ü 3 H 1 3 C5 WF A,s Au Ai 3 R Y High-Speed BiCMOS 1M 1M xi ECL Static RAM ■ Description ■ The LH101504/LH101510 is a 256K/1M-bit high speed


    OCR Scan     		PDF LH101504 LH101510 LH101504/LH101510 256K/1M-bit 742S6 9660t LH521008

    LH521007AK-20

    Abstract: No abstract text available
    Text: STATIC RAM ☆ New product ★ Under development STATIC RAMs ♦ Features • The product lineup includes a wide variety of bit configurations x4, x8, x l6 , x l8 , x32 . • High-speed synchronous devices for the secondary cache memory are available for use with low-voltage, lowpower CPUs idpal for portable equipment.


    OCR Scan     		PDF LH5116SN LH5164AVN/AVT LH5164AV3HN 24SOP 28S0P/28TS0P LH5268A/AN/AD-1 52256C -70LIÆ 710LL LH521007AK-20

    MB821

    Abstract: LH521002K-20 KM641001-20 UPD431004LE-25 UPD431004LE-20 KM641001-25 KM641001-35 LH521002K-25 t5c1 t5c1005
    Text: - 145 m s it £ ÎS Â ÏE H OC RAM 2 6 2 1 4 4 x 4 ) IM CMOS S t a t i c X 'i 7 f y 7 # t ì TAAC sax (ns) TCAC •ax (ns) TOE max TOH nin (ns) (ns) TOD nax (ns) TWP tin (ns) % TDS rain TDH TWD min (ni;) (ns) (ns) TWR œax (ns) VC'D or V C C (V) 28 PI N


    OCR Scan     		PDF 62144x4) 28PIN 1M624257JP-45 HM624257I JP-35 HHB24257LJP-45 KM641001-208 MCM6229A-30 T5C1005-25 HT5C1005-35 MB821 LH521002K-20 KM641001-20 UPD431004LE-25 UPD431004LE-20 KM641001-25 KM641001-35 LH521002K-25 t5c1 t5c1005

    LHS168

    Abstract: LH52252A LH52252
    Text: V .J 1 íVt! Static RAMs ★Under development Process Capacity Model No. Configuration Access time ns 70 -I 16k 2k Package 90 100 120 LH5116 J— I. 24 24 24 LH5116H 3 -T 24 24 24 - Z ÏÏ-J 1 24 24 24 C E , C S c o n tro l Data retention current : 0.2 pAjMAXj j


    OCR Scan     		PDF LH5116 LH5116H LH5116S LH5117 LH511 LH5118 LH5118H LH52252A LH52253 LH521002A LHS168 LH52252