7C13 Search Results

64KX32

Abstract: 7C13 CY7C1329
Contextual Info: fax id: 1080 1CY 7C13 29 7C1329 PRELIMINARY 64K x 32 Synchronous-Pipelined Cache RAM Features Functional Description • Low 1.65 mW standby power (f=0, L version) The 7C1329 is 3.3V 64K by 32 synchronous-pipelined cache SRAM designed to support zero wait state secondary

7C13

Abstract: CY7C1335
Contextual Info: fax id: 1045 1CY 7C13 35 PRELIMINARY 7C1335 32K x 32 Synchronous-Pipelined Cache RAM Features Functional Description • Low 660 µW standby power (f=0, L version) The 7C1335 is 3.3V 32K by 32 synchronous-pipelined cache SRAM designed to support zero wait state secondary

Contextual Info: 7C132/7C136 CY7C142/CY7C146 CYPRESS SEMICONDUCTOR 2K x 8 Dual-Port Static RAM Features Functional Description • 0.8-raicron CMOS for optimum speed/power • BÜSŸ output flag on 7C132/ 7C136; BUSY input on CY7C142/CY7C146 The 7C132/CY 7C136/CY7C142/

TLA700

Abstract: CY7C1351B LA-BGA-7C1351-S-B-01
Contextual Info: LA-BGA-7C1351-S-B-01 Drawing 1.8100" [45.974mm] Top View 1.3500" [34.290mm] 2 0.480" [12.186mm] 1 0.0625" [1.588mm] Side View 0.6795" [17.259mm] Fully Plugged 1 2 3 3 Substrate: 1.59mm ±0.18mm [0.0625" ±0.007"] FR4/G10 or equivalent high temp material. 17µm [1/2 oz.] Cu clad. SnPb plating.

CY7C1302V25

Abstract: CY7C1302V25-133BZC
Contextual Info: yy 7c1302V25: Rev 1.0 Revised: February 15, 2000 7C1302V25 Advanced Information 9-Mb Pipelined SRAM with QDR Architecture Features Functional Description • Separate Independent Read and Write Data Ports — Supports concurrent transactions • 167-MHz Clock for High Bandwidth

7C130

Abstract: L1314
Contextual Info: 7C130/7C131 CY7C140/CY7C141 _ 1024 x 8 Dual-Port Static RAM aT ^ p -¿r CYPRESS ^ SEMICONDUCTOR E ach p o rt has independent control pins; chip enable C E , w rite enable (RyW), and output The CY 7C130/7C131/CY7C140/ enable (O E ). TVvo flags are p rovided on each

7C13

Abstract: CY7C133 CY7C143 IDT7133 IDT7143 bit-slice C1335
Contextual Info: fax id: 5202 1CY 7C13 3 7C133 CY7C143 2K x 16 Dual-Port Static RAM Features Functional Description • True Dual-Ported memory cells which allow simultaneous reads of the same memory location • 2K x 16 organization • 0.65-micron CMOS for optimum speed/power

Contextual Info: 7c1399: Monday, November 16,1992 Revision: Wednesday, January 6,1993 7C1399 ADVANCED INFORMATION CYPRESS t SEMICONDUCTOR = ' 3.3V 32Kx 8 Static RAM • Automatic power-down when deselected Features • Single 3 3 ± 0.3V power supply • H ighspeed — 15 ns

j6916

Abstract: 7C13 CY7C132 CY7C136 CY7C146 C13220 CY7C136-55NC Master Selection Guide
Contextual Info: fax id: 5201 1CY 7C13 2/ CY7C1 36 7C132/7C136 CY7C142/CY7C146 2Kx8 Dual-Port Static RAM Features Functional Description • True Dual-Ported memory cells which allow simultaneous reads of the same memory location • 2K x 8 organization • 0.65-micron CMOS for optimum speed/power

c1399

Abstract: C1399 transistor 7C13 CY7C1399 C13997
Contextual Info: 1CY 7C13 99 7C1399 32K x 8 3.3V Static RAM Features • Single 3.3V power supply • Ideal for low-voltage cache memory applications • High speed — 12/15 ns • Low active power — 255 mW max. • Low CMOS standby power (L) — 180 µW (max.), f=fMAX

verilog for SRAM 512k word 16bit

Abstract: CY62512V CYM74P436 192-Macrocell 62128 sram 7C1350 Triton P54C palce16v8 programming guide 7C168A intel 16k 8bit RAM chip
Contextual Info: Product Selector Guide Static RAMs Organization/Density Density X1 X4 4K X8 X9 X16 X18 X32 X36 7C148 7C149 7C150 16K 7C167A 7C168A 7C128A 6116 64K to 72K 7C187 7C164 7C166 7C185 6264 7C182 256K to 288K 7C197 7C194 7C195 7C199 7C1399/V 62256/V 62256V25 62256V18

j6916

Abstract: idt7132 CY7C136-55JC cy7c136 7C13 CY7C132 CY7C146 c1322 C13220 cy7c146-35jc
Contextual Info: fax id: 5201 1CY 7C13 2/ CY7C1 36 7C132/7C136 CY7C142/CY7C146 2Kx8 Dual-Port Static RAM Features Functional Description • True Dual-Ported memory cells which allow simultaneous reads of the same memory location • 2K x 8 organization • 0.65-micron CMOS for optimum speed/power

Contextual Info: THIS SPEC IS OBSOLETE Spec No: 001-07165 Spec Title: 7C1313CV18/7C1315CV18, 18-MBIT QDR R II SRAM 4-WORD BURST ARCHITECTURE Sunset Owner: Jayasree Nayar (NJY) Replaced by: NONE 7C1313CV18 7C1315CV18 18-Mbit QDR II SRAM 4-Word Burst Architecture 18-Mbit QDR® II SRAM 4-Word Burst Architecture

HA 13645

Abstract: acr38
Contextual Info: 7C132/7C136 CY7C142/CY7C146 CYPRESS SEMICONDUCTOR 2K x 8 Dual-Port Static RAM Features Functional Description • 0.8-micron CM OS for optimum speed/power • BUSY output flag on 7C132/ 7C136; BUSY input on CY7C142/CY7C146 The 7C132/CY 7C136/CY7C142/

7C13

Abstract: CY7C1337
Contextual Info: fax id: 1076 1CY 7C13 37 PRELIMINARY 7C1337 32K x 32 Synchronous-Pipelined Cache RAM Features Functional Description • Low 660 µW standby power (f=0, L version) • Supports 117-MHz bus operations with zero wait states • Fully registered inputs and outputs for pipelined operation

C1399

Abstract: 7C13 CY7C1399V
Contextual Info: 1CY 7C13 99 V 7C1399V 32K x 8 3.0V Static RAM Features • Single 3.0V power supply • Ideal for low-voltage cache memory applications • High speed — 12/15 ns • Low active power — 198 mW max. • Low CMOS standby power (L) — 165 mW (max.), f=fMAX

64KX32

Abstract: 7C13 7C1334-100 7C1334-133 7C1334-50 7C1334-80 CY7C1334 CY7C1334-50AC
Contextual Info: fax id: 1084 1CY 7C13 35 7C1334 PRELIMINARY 64Kx32 Pipelined SRAM with NoBL Architecture Features Functional Description • Supports 133-MHz bus operations with zero wait states—Data is transferred on every clock The 7C1334 is a 3.3V 64K by 32 synchronous-pipelined

CEL9200

Abstract: CY7C1019 CY7C1021 CY7C1021V sumitomo silver epoxy
Contextual Info: Cypress Semiconductor Qualification Report QTP# 97416 VERSION 1.0 June, 1998 1 Meg SRAM, R42D Technology, Fab 4 Qualification CY7C1021V 64K x 16 Static RAM CY7C1019V 128K x 8 Static RAM Cypress Semiconductor, Inc. 1 Meg SRAM - R42D Technology - Fab 4 Device: CY7C1021V/CY7C1019V 7C1321D/7C1319D

C1384

Abstract: C1383 c138 transistor cy7c139-25jc C138-8 7C13 CY7C138 CY7C139 C138-4 C1385
Contextual Info: fax id: 5204 1CY 7C13 9 7C138 7C139 4K x 8/9 Dual-Port Static RAM Features • True Dual-Ported memory cells which allow simultaneous reads of the same memory location • 4K x 8 organization 7C138 • 4K x 9 organization (7C139) • 0.65-micron CMOS for optimum speed/power

64KX32

Abstract: 7C13 CY7C1330
Contextual Info: fax id: 1081 1CY 7C13 30 7C1330 PRELIMINARY 64K x 32 Synchronous-Pipelined Cache RAM Features Functional Description • Low 1.65 mW standby power (f=0, L version) • Supports 117-MHz bus operations with zero wait states • Fully registered inputs and outputs for pipelined operation

7C13

Abstract: CY7C1342 CY7C135 7c1342
Contextual Info: fax id: 5203 1CY 7C13 42 7C135 7C1342 4K x 8 Dual-Port Static RAMs and 4K x 8 Dual-Port Static RAM with Semaphores Features • True Dual-Ported memory cells which allow simultaneous reads of the same memory location • 4K x 8 organization • 0.65-micron CMOS for optimum speed/power

C1388

Contextual Info: 7c1388: Friday, November 13,1992 Revision: Wednesday, January 6,1993 2 3 1993 5SEE7 .s i CYPRESS ~—'' ^ SEMICONDUCTOR • Automatic power-down when deselected Features • Single 3 3 ± 0.3V power supply • Highspeed — 20 ns • Low active power — 235 mW

CY7C1351B

Abstract: PB-BGA-7C1351-01 TLA700
Contextual Info: PB-BGA-7C1351-01 Drawing 1.8100" [45.974mm] Top View 1.3500" [34.290mm] 0.480" [12.186mm] 0.0625" [1.588mm] Side View 2 1 1 2 Substrate: 1.59mm ±0.18mm [0.0625" ±0.007"] FR4/G10 or equivalent high temp material. 17µm [1/2 oz.] Cu clad. SnPb plating. Pins: shell material- Brass; shell finish10µ" Gold over 50µ" Nickel min. .

CY7C1339

Contextual Info: fax id: 1109 PRELIMINARY 7C1339 128K x 32 Synchronous-Pipelined Cache RAM Features Functional Description • Low 1.65 mW standby power (f=0, L version) The 7C1339 is a 3.3V 128K by 32 synchronous-pipelined cache SRAM designed to support zero wait state secondary