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    Infineon Technologies AG CY7C1460KV25-250AXC

    IC SRAM 36MBIT PAR 100TQFP
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    DigiKey CY7C1460KV25-250AXC Tray 474 1
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    Mouser Electronics CY7C1460KV25-250AXC
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    Infineon Technologies AG CY7C1461KV33-133AXI

    IC SRAM 36MBIT PARALLEL 100TQFP
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    DigiKey CY7C1461KV33-133AXI Tray 136 1
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    Rochester Electronics CY7C1461KV33-133AXI 1,800 1
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    Cypress Semiconductor CY7C1463KV33-133AXC

    NO WARRANTY
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    DigiKey CY7C1463KV33-133AXC Tray 25 1
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    Flip Electronics CY7C1463KV33-133AXC 3,029
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    Infineon Technologies AG CY7C146-25JXC

    IC SRAM 16KBIT PARALLEL 52PLCC
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    Rochester Electronics LLC CY7C146-25JXC

    IC SRAM 16KBIT PARALLEL 52PLCC
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    DigiKey CY7C146-25JXC Tube 66
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    Find more CY7C146 price and stock on Findchips.com

    CY7C146 Datasheets (210)

    Part ECAD Model Manufacturer Description Curated Datasheet Type PDF
    CY7C146 Cypress Semiconductor 2Kx8 Dual-Port Static RAM Original PDF
    CY7C146 Unknown 2Kx8 Dual-Port Static RAM Original PDF
    CY7C1460AV25 Cypress Semiconductor 36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined SRAM with NoBL Architecture Original PDF
    CY7C1460AV25-167AXC Cypress Semiconductor Memory, Integrated Circuits (ICs), IC SRAM 36MBIT 167MHZ 100TQFP Original PDF
    CY7C1460AV25-167AXC Cypress Semiconductor 36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined SRAM with NoBL Architecture; Architecture: NoBL, Pipeline; Density: 36 Mb; Organization: 1Mb x 36; Vcc (V): 2.4 to 2.6 V Original PDF
    CY7C1460AV25-167AXCT Cypress Semiconductor Memory, Integrated Circuits (ICs), IC SRAM 36MBIT 167MHZ 100TQFP Original PDF
    CY7C1460AV25-167AXCT Cypress Semiconductor 36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined SRAM with NoBL Architecture; Architecture: NoBL, Pipeline; Density: 36 Mb; Organization: 1Mb x 36; Vcc (V): 2.4 to 2.6 V Original PDF
    CY7C1460AV25-167BZC Cypress Semiconductor Memory, Integrated Circuits (ICs), IC SRAM 36MBIT 167MHZ 165FBGA Original PDF
    CY7C1460AV25-167BZC Cypress Semiconductor 36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined SRAM with NoBL Architecture; Architecture: NoBL, Pipeline; Density: 36 Mb; Organization: 1Mb x 36; Vcc (V): 2.4 to 2.6 V Original PDF
    CY7C1460AV25-167BZCT Cypress Semiconductor Memory, Integrated Circuits (ICs), IC SRAM 36MBIT 167MHZ 165FBGA Original PDF
    CY7C1460AV25-167BZCT Cypress Semiconductor 36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined SRAM with NoBL Architecture; Architecture: NoBL, Pipeline; Density: 36 Mb; Organization: 1Mb x 36; Vcc (V): 2.4 to 2.6 V Original PDF
    CY7C1460AV25-167BZXI Cypress Semiconductor Memory, Integrated Circuits (ICs), IC SRAM 36MBIT 167MHZ 165FBGA Original PDF
    CY7C1460AV25-167BZXI Cypress Semiconductor 36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined SRAM with NoBL Architecture; Architecture: NoBL, Pipeline; Density: 36 Mb; Organization: 1Mb x 36; Vcc (V): 2.4 to 2.6 V Original PDF
    CY7C1460AV25-200BZC Cypress Semiconductor 36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined SRAM with NoBL Architecture; Architecture: NoBL, Pipeline; Density: 36 Mb; Organization: 1Mb x 36; Vcc (V): 2.4 to 2.6 V Original PDF
    CY7C1460AV25-200BZI Cypress Semiconductor Memory, Integrated Circuits (ICs), IC SRAM 36MBIT 200MHZ 165FBGA Original PDF
    CY7C1460AV25-200BZI Cypress Semiconductor 36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined SRAM with NoBL Architecture; Architecture: NoBL, Pipeline; Density: 36 Mb; Organization: 1Mb x 36; Vcc (V): 2.4 to 2.6 V Original PDF
    CY7C1460AV25-200BZXC Cypress Semiconductor 36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined SRAM with NoBL Architecture; Architecture: NoBL, Pipeline; Density: 36 Mb; Organization: 1Mb x 36; Vcc (V): 2.4 to 2.6 V Original PDF
    CY7C1460AV25-200BZXI Cypress Semiconductor Memory, Integrated Circuits (ICs), IC SRAM 36MBIT 200MHZ 165FBGA Original PDF
    CY7C1460AV25-200BZXI Cypress Semiconductor 36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined SRAM with NoBL Architecture; Architecture: NoBL, Pipeline; Density: 36 Mb; Organization: 1Mb x 36; Vcc (V): 2.4 to 2.6 V Original PDF
    CY7C1460AV25-250 Cypress Semiconductor 36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined SRAM with NoBL Architecture Original PDF
    ...

    CY7C146 Datasheets Context Search

    Catalog Datasheet MFG & Type PDF Document Tags

    Untitled

    Abstract: No abstract text available
    Text: CY7C1460AV25 CY7C1462AV25 36-Mbit 1 M x 36/2 M × 18 Pipelined SRAM with NoBL Architecture 36-Mbit (1 M × 36/2 M × 18) Pipelined SRAM with NoBL™ Architecture Features Functional Description • Pin-compatible and functionally equivalent to ZBT™


    Original     		PDF CY7C1460AV25 CY7C1462AV25 36-Mbit CY7C1460AV25/CY7C1462AV25 CY7C14s

    Untitled

    Abstract: No abstract text available
    Text: CY7C146-55JC 1/3 IL08 * C-MOS 16K (2048 x 8)-BIT STATIC RAM R IN 47 A10 48 INT R OUT 49 BUSY R IN 50 R/W R IN R IN 51 CE V DD (+5V) 52 L IN 1 CE 2 R/W L IN L IN 5 A10 3 BUSY L IN L IN 6 OE 4 INT L OUT L IN 7 A0 - TOP VIEW - 46 OE A1 L IN 8 A2 L IN


    Original     		PDF CY7C146-55JC

    CY7C1461V25

    Abstract: CY7C1463V25 CY7C1465V25
    Text: CY7C1461V25 CY7C1463V25 CY7C1465V25 PRELIMINARY 1M x 36/2M x 18/512K x 72 Flow-Thru SRAM with NoBL Architecture Features • Zero Bus Latency, no dead cycles between Write and Read cycles •Supports 133-MHz bus operations •1M x 36/2M × 18/512K × 72 common I/O


    Original     		PDF CY7C1461V25 CY7C1463V25 CY7C1465V25 36/2M 18/512K 133-MHz 36/2M 18/512K 150-MHz CY7C1461V25 CY7C1463V25 CY7C1465V25

    CY7C132

    Abstract: CY7C136 CY7C146
    Text: CY7C132/CY7C136 CY7C142/CY7C146 2K x 8 Dual-Port Static RAM Features Functional Description • True Dual-Ported memory cells which allow simultaneous reads of the same memory location The CY7C132/CY7C136/CY7C142 and CY7C146 are high-speed CMOS 2K by 8 dual-port static RAMs. Two ports


    Original     		PDF CY7C132/CY7C136 CY7C142/CY7C146 CY7C132/CY7C136/CY7C142 CY7C146 CY7C132/ CY7C136 16-bit CY7C132

    Untitled

    Abstract: No abstract text available
    Text: CY7C1460AV33 CY7C1462AV33 36-Mbit 1 M x 36/2 M × 18 Pipelined SRAM with NoBL Architecture 36-Mbit (1 M × 36/2 M × 18) Pipelined SRAM with NoBL™ Architecture Features Functional Description • Pin compatible and functionally equivalent to ZBT ■


    Original     		PDF CY7C1460AV33 CY7C1462AV33 36-Mbit

    CY7C136-55NI

    Abstract: cy7c136 CY7C132 CY7C142 CY7C146 CY7C146-15NC CY7C136-25JXC CY7C136-55NC
    Text: CY7C132, CY7C136 CY7C136A, CY7C142, CY7C146 2K x 8 Dual-Port Static RAM Features Functional Description • True dual-ported memory cells that enable simultaneous reads of the same memory location ■ 2K x 8 organization ■ 0.65 micron CMOS for optimum speed and power


    Original     		PDF CY7C132, CY7C136 CY7C136A, CY7C142, CY7C146 CY7C136, CY7C136-55NI cy7c136 CY7C132 CY7C142 CY7C146 CY7C146-15NC CY7C136-25JXC CY7C136-55NC

    CY7C1464AV33-167BGI

    Abstract: CY7C1460AV33 CY7C1462AV33 CY7C1464AV33 CY7C1462AV33-200AXC
    Text: CY7C1460AV33 CY7C1462AV33 CY7C1464AV33 36-Mbit 1M x 36/2M x 18/512K x 72 Pipelined SRAM with NoBL Architecture Features Functional Description • Pin-compatible and functionally equivalent to ZBT™ • Supports 250-MHz bus operations with zero wait states


    Original     		PDF CY7C1460AV33 CY7C1462AV33 CY7C1464AV33 36-Mbit 36/2M 18/512K 250-MHz CY7C1460AV33, CY7C1462AV33 CY7C1464AV33-167BGI CY7C1460AV33 CY7C1464AV33 CY7C1462AV33-200AXC

    CY7C1464AV33-167BGI

    Abstract: CY7C1460AV33 CY7C1462AV33 CY7C1464AV33 cypress nobl 1-Mbit sram
    Text: CY7C1460AV33 CY7C1462AV33 CY7C1464AV33 36-Mbit 1M x 36/2M x 18/512K x 72 Pipelined SRAM with NoBL Architecture Features Functional Description • Pin-compatible and functionally equivalent to ZBT™ • Supports 250-MHz bus operations with zero wait states


    Original     		PDF CY7C1460AV33 CY7C1462AV33 CY7C1464AV33 36-Mbit 36/2M 18/512K 250-MHz CY7C1460AV33, CY7C1462AV33 CY7C1464AV33-167BGI CY7C1460AV33 CY7C1464AV33 cypress nobl 1-Mbit sram

    CY7C1462AV25

    Abstract: CY7C1460AV25 CY7C1464AV25
    Text: CY7C1460AV25 CY7C1462AV25 CY7C1464AV25 36-Mbit 1M x 36/2M x 18/512K x 72 Pipelined SRAM with NoBL Architecture Features Functional Description • Pin-compatible and functionally equivalent to ZBT™ • Supports 250-MHz bus operations with zero wait states


    Original     		PDF CY7C1460AV25 CY7C1462AV25 CY7C1464AV25 36-Mbit 36/2M 18/512K 250-MHz CY7C1460AV25, CY7C1462AV25 CY7C1460AV25 CY7C1464AV25

    Untitled

    Abstract: No abstract text available
    Text: CY7C1460AV25 CY7C1462AV25 CY7C1464AV25 36-Mbit 1M x 36/2M x 18/512K x 72 Pipelined SRAM with NoBL Architecture Features Functional Description • Pin-compatible and functionally equivalent to ZBT™ • Supports 250-MHz bus operations with zero wait states


    Original     		PDF CY7C1460AV25 CY7C1462AV25 CY7C1464AV25 36-Mbit 36/2M 18/512K 250-MHz 200-MHz 167-MHz

    Untitled

    Abstract: No abstract text available
    Text: CY7C1460AV33 CY7C1462AV33 36-Mbit 1 M x 36/2 M × 18 Pipelined SRAM with NoBL Architecture 36-Mbit (1 M × 36/2 M × 18) Pipelined SRAM with NoBL™ Architecture Features Functional Description • Pin compatible and functionally equivalent to ZBT ■


    Original     		PDF CY7C1460AV33 CY7C1462AV33 36-Mbit CY7C1460AV33/CY7C1462AV33

    CY7C1461AV33

    Abstract: CY7C1463AV33 CY7C1465AV33 K1061 u946 B897
    Text: CY7C1461AV33 CY7C1463AV33 CY7C1465AV33 PRELIMINARY 36-Mbit 1M x 36/2 M x 18/512K x 72 Flow-Through SRAM with NoBL Architecture Features • JTAG boundary scan for BGA and fBGA packages • No Bus Latency™ (NoBL™) architecture eliminates dead cycles between write and read cycles.


    Original     		PDF CY7C1461AV33 CY7C1463AV33 CY7C1465AV33 36-Mbit 18/512K 133-MHz 100-MHz CY7C1461AV33 CY7C1463AV33 CY7C1465AV33 K1061 u946 B897

    CY7C1460AV25

    Abstract: CY7C1462AV25 CY7C1464AV25
    Text: CY7C1460AV25 CY7C1462AV25 CY7C1464AV25 36-Mbit 1 M x 36/2 M × 18/512 K × 72 Pipelined SRAM with NoBL Architecture 36-Mbit (1 M × 36/2 M × 18/512 K × 72) Pipelined SRAM with NoBL™ Architecture Features Functional Description • Pin-compatible and functionally equivalent to ZBT™


    Original     		PDF CY7C1460AV25 CY7C1462AV25 CY7C1464AV25 36-Mbit 250-MHz CY7C1460AV25 CY7C1462AV25 CY7C1464AV25

    CY7C1461AV33

    Abstract: CY7C1463AV33 CY7C1465AV33
    Text: CY7C1461AV33 CY7C1463AV33 CY7C1465AV33 36-Mbit 1M x 36/2 M x 18/512K x 72 Flow-Through SRAM with NoBL Architecture Functional Description[1] Features • No Bus Latency™ (NoBL™) architecture eliminates dead cycles between write and read cycles • Supports up to 133-MHz bus operations with zero wait


    Original     		PDF CY7C1461AV33 CY7C1463AV33 CY7C1465AV33 36-Mbit 18/512K 133-MHz CY7C1461AV33/CY7C1463AV33/CY7C1465AV33 36/2M CY7C1461AV33 CY7C1463AV33 CY7C1465AV33

    05353

    Abstract: CY7C1460AV33 CY7C1462AV33 CY7C1464AV33
    Text: CY7C1460AV33 CY7C1462AV33 CY7C1464AV33 36 Mbit 1M x 36/2M x 18/512K x 72 Pipelined SRAM with NoBL Architecture Features Functional Description • Pin compatible and functionally equivalent to ZBT ■ Supports 250 MHz Bus Operations with Zero Wait States


    Original     		PDF CY7C1460AV33 CY7C1462AV33 CY7C1464AV33 36/2M 18/512K CY7C1460AV33/CY7C1462AV33/CY7C1464AV33 05353 CY7C1460AV33 CY7C1462AV33 CY7C1464AV33

    CY7C1461AV33

    Abstract: CY7C1463AV33 CY7C1465AV33
    Text: CY7C1461AV33 CY7C1463AV33, CY7C1465AV33 36-Mbit 1 M x 36/2 M × 18/512 K × 72 Flow-Through SRAM with NoBL Architecture 36-Mbit (1 M × 36/2 M × 18/512 K × 72) Flow-Through SRAM with NoBL™ Architecture Features Functional Description • No Bus Latency™ (NoBL™) architecture eliminates dead


    Original     		PDF CY7C1461AV33 CY7C1463AV33, CY7C1465AV33 36-Mbit CY7C1461AV33 CY7C1463AV33 CY7C1465AV33

    250ac to 30 v ac

    Abstract: CY7C1462V25 CY7C1464V25 CY7C1460V25
    Text: CY7C1460V25 CY7C1462V25 CY7C1464V25 PRELIMINARY 1M x 36/2M x 18/512K x 72 Pipelined SRAM with NoBL Architecture Features • Zero Bus Latency, no dead cycles between write and read cycles • Fast clock speed: 250, 200, and 167 MHz • Fast access time: 2.7, 3.0 and 3.5 ns


    Original     		PDF CY7C1460V25 CY7C1462V25 CY7C1464V25 36/2M 18/512K CY7C1460V25 CY7C1462V25 250ac to 30 v ac CY7C1464V25

    C13220

    Abstract: C1328 C1327 CY7C132 CY7C136 CY7C146 C1323 CY7C136-55NC
    Text: CY7C132/CY7C136 CY7C142/CY7C146 2K x 8 DualĆPort Static RAM output enable OE . BUSY flags are proĆ vided on each port. In addition, an interĆ rupt flag (INT) is provided on each port of the 52Ćpin LCC and PLCC versions. BUSY signals that the port is trying to access the


    Original     		PDF CY7C132/CY7C136 CY7C142/CY7C146 52pin CY7C132/ CY7C136; C13220 C1328 C1327 CY7C132 CY7C136 CY7C146 C1323 CY7C136-55NC

    Untitled

    Abstract: No abstract text available
    Text: fax id: 5201 CY7C132/CY7C136 CY7C142/CY7C146 W CYPRESS 2Kx8 Dual-Port Static RAM Features Functional Description True Dual-Ported memory cells which allow sim ulta­ neous reads of the same mem ory location 2K x 8 organization 0.65-micron CMOS for optimum speed/power


    OCR Scan     		PDF CY7C132/CY7C136 CY7C142/CY7C146 65-micron CY7C132/CY7C136 CY7C132/CY7C136; 52-pin 48-pin CY7C132/142)

    Untitled

    Abstract: No abstract text available
    Text: CY7C132/CY7C136 CY7C142/CY7C146 CYPRESS SEMICONDUCTOR 2K x 8 Dual-Port Static RAM Features Functional Description • 0.8-raicron CMOS for optimum speed/power • BÜSŸ output flag on CY7C132/ CY7C136; BUSY input on CY7C142/CY7C146 The CY7C132/CY 7C136/CY7C142/


    OCR Scan     		PDF CY7C132/CY7C136 CY7C142/CY7C146 CY7C132/ CY7C136; CY7C132/CY 7C136/CY7C142/ 7C146 7C136

    Z1213

    Abstract: CY7C132 CY7C136 CY7C146 zl12
    Text: bSE » CYPRESS SEMICONDUCTOR SSÖ'lbbE 0 0 0 ^ 7 4 7 ISb I CYP CY7C132/CY7C136 CY7C142/CY7C146 CYPRESS SEMICONDUCTOR 2K x 8 Dual-Port Static RAM output enable OE . BUSY flags are pro­ vided on each port. In addition, an interrupt Functional Description Features


    OCR Scan     		PDF CY7C132/CY7C136 CY7C142/CY7C146 CY7C142/CY7C146 CY7C132/ CY7C136; 52-pin CY7C132/CY7C136/CY7C142/ CY7C146 Z1213 CY7C132 CY7C136 zl12

    C-136B

    Abstract: No abstract text available
    Text: CY7C132/CY7C136 CY7C142/CY7C146 CYPRESS 2K x 8 Dual-Port Static RAM F ea tu res F u n ctio n al D escrip tio n • 0 .8 -m icro n C M O S for optim u m speed/ pow er • A u to m atic power-down • T T L com p atib le • C ap ab le o f w ith stan d in g g re a te r th an


    OCR Scan     		PDF CY7C132/CY7C136 CY7C142/CY7C146 C-136B

    30l3l

    Abstract: No abstract text available
    Text: CY7C132/CY7C136 CY7C142/CY7C146 CYPRESS SEMICONDUCTOR F eatures F unctional D escription • 0.8-micron CMOS for optimum speed/power • Automatic power-down • TTL compatible • Capable of withstanding greater than 2001V electrostatic discharge • Fully asynchronous operation


    OCR Scan     		PDF CY7C132/CY7C136 CY7C142/CY7C146 MASTERCY7CI32/CY7C136 CY7C132/ CY7C136; 52-pin CY7C142/CY7C146 30l3l

    HA 13645

    Abstract: No abstract text available
    Text: fax id: 5201 CY7C132/CY7C136 CY7C142/CY7C146 2Kx8 Dual-Port Static RAM Featu res Functional Description • True Dual-Ported memory cells which allow sim ulta­ neous reads of the same memory location • 2K x 8 organization • 0.65-micron CMOS for optimum speed/power


    OCR Scan     		PDF CY7C132/CY7C136 CY7C142/CY7C146 65-micron Y7C142/CY7C146 CY7C132/CY7C136; CY7C142/CY7C146 52-pin 48-pin CY7C132/142) HA 13645