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    7C130 Search Results

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    7C130 Price and Stock

    Vishay Semiconductors BZD27C130P-E3-08

    DIODE ZENER 130V 800MW DO219AB
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    DigiKey BZD27C130P-E3-08 Cut Tape 35,176 1
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    BZD27C130P-E3-08 Digi-Reel 35,176 1
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    BZD27C130P-E3-08 Reel 30,000 3,000
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    Vishay Semiconductors BZD27C130P-HE3-08

    DIODE ZENER 130V 800MW DO219AB
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    DigiKey BZD27C130P-HE3-08 Cut Tape 18,366 1
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    BZD27C130P-HE3-08 Digi-Reel 18,366 1
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    BZD27C130P-HE3-08 Reel 15,000 3,000
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    KEMET Corporation C317C130J5G5TA7301

    CAP CER 13PF 50V C0G/NP0 RADIAL
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    KEMET Corporation C317C130J5G5TA

    CAP CER 13PF 50V C0G/NP0 RADIAL
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    Avnet Abacus C317C130J5G5TA 25 Weeks 1,500
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    KEMET Corporation C317C130JDG5TA

    CER CAP
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    DigiKey C317C130JDG5TA Bulk 498 1
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    Mouser Electronics C317C130JDG5TA 175
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    7C130 Datasheets Context Search

    Catalog Datasheet MFG & Type PDF Document Tags

    CY7C1302V25

    Abstract: CY7C1302V25-133BZC
    Text: yy 7c1302V25: Rev 1.0 Revised: February 15, 2000 7C1302V25 Advanced Information 9-Mb Pipelined SRAM with QDR Architecture Features Functional Description • Separate Independent Read and Write Data Ports — Supports concurrent transactions • 167-MHz Clock for High Bandwidth


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    PDF 7c1302V25: CY7C1302V25 167-MHz CY7C1302V25 CY7C1302V25-133BZC

    CY7C1304V25

    Abstract: No abstract text available
    Text: 5 7C1304V25 Advanced Information 9-Mb Pipelined SRAM with QDR Architecture Features Functional Description • Separate Independent Read and Write Data Ports — Supports concurrent transactions • 167 MHz Clock for High Bandwidth — 2.5 ns Clock-to-Valid access time


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    PDF CY7C1304V25 CY7C1304V25

    CY7C1304V25

    Abstract: No abstract text available
    Text: 304V25 7C1304V25 Advanced Information 9-Mb Pipelined SRAM with QDR Architecture Features Functional Description • Separate Independent Read and Write Data Ports — Supports concurrent transactions • 167 MHz Clock for High Bandwidth — 2.5 ns Clock-to-Valid access time


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    PDF 304V25 CY7C1304V25 CY7C1304V25

    ATPA

    Abstract: 7130SA100P 24l01 7C263/4-35C 7164S15Y cy9122-25 7133SA35J 7142sa55 7130sa55p cy2149-45c
    Text: Product Line Cross Reference CYPRESS CYPRESS CYPRESS CYPRESS CYPRESS CY2147-35C CY7C147-35C CY7C147-45C CY7C147-35C CY91L22-35C CY7C122-35C CY2147-45C CY2147-35C CY7C148-35C CY7C148-25C+ CY91L22-45C CY93L422AC CY2147-45C CY7C147-45C CY7C148-45C CY7C148-35C


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    PDF CY2147-35C CY7C147-35C CY7C147-45C CY91L22-35C CY7C122-35C CY2147-45C CY7C148-35C CY7C148-25C+ ATPA 7130SA100P 24l01 7C263/4-35C 7164S15Y cy9122-25 7133SA35J 7142sa55 7130sa55p cy2149-45c

    PLCC-52

    Abstract: CY7C130 CY7C131 CY7C140 CY7C141 CY7C131-25JC CY7C131-35J Z1014
    Text: 7C130, 7C130A CY7C131, CY7C131A CY7C140, CY7C141 1K x 8 Dual-Port Static RAM Features Functional Description • True dual-ported memory cells, which allow simultaneous reads of the same memory location ■ 1K x 8 organization ■ 0.65 micron CMOS for optimum speed and power


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    PDF CY7C130, CY7C130A CY7C131, CY7C131A CY7C140, CY7C141 CY7C130/130A/CY7C131/131A/CY7C140 CY7C130/130A/ CY7C131/131A PLCC-52 CY7C130 CY7C131 CY7C140 CY7C141 CY7C131-25JC CY7C131-35J Z1014

    7C13135

    Abstract: CY7C140-35PC 7C130 CY7C130 CY7C131 CY7C140 CY7C141
    Text: 7C130/CY7C131 CY7C140/CY7C141 1K x 8 Dual-Port Static RAM Features Functional Description • True Dual-Ported memory cells which allow simultaneous reads of the same memory location The 7C130/CY7C131/CY7C140 and CY7C141 are high-speed CMOS 1K by 8 dual-port static RAMs. Two ports


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    PDF CY7C130/CY7C131 CY7C140/CY7C141 CY7C130/CY7C131/CY7C140 CY7C141 CY7C130/ CY7C131 CY7C140/CY7C141 16-bit 7C13135 CY7C140-35PC 7C130 CY7C130 CY7C140

    CY7C1305V25-167BZC

    Abstract: No abstract text available
    Text: 7C1305V25 7C1307V25 PRELIMINARY 18-Mb Burst of 4 Pipelined SRAM with QDR Architecture Features Functional Description • Separate independent Read and Write data ports • 2.5V core power supply with HSTL Inputs and Outputs The 7C1305V25/7C1307V25 are 2.5V Synchronous


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    PDF CY7C1305V25 CY7C1307V25 18-Mb 167-MHz BB165D BB165A CY7C1305V25-167BZC

    CY7C

    Abstract: CY7C130 CY7C131 CY7C140 CY7C141
    Text: 7C130, 7C130A CY7C131, CY7C131A 1 K x 8 Dual-Port Static RAM 1 K × 8 Dual-Port Static RAM Features Functional Description • True dual-ported memory cells, which allow simultaneous reads of the same memory location ■ 1 K × 8 organization ■ 0.65 micron CMOS for optimum speed and power


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    PDF CY7C130, CY7C130A CY7C131, CY7C131A CY7C130/130A/CY7C131/131A/CY7C140 CY7C141 CY7C130/130A/CY7C131/131A CY7C CY7C130 CY7C131 CY7C140 CY7C141

    CY7C1304V25

    Abstract: No abstract text available
    Text: 7C1304V25 9-Mb Pipelined SRAM with QDR Architecture Features Functional Description • Separate independent Read and Write data ports — Supports concurrent transactions • 167 MHz Clock for high bandwidth — 2.5 ns Clock-to-Valid access time • 4-Word burst for reducing address bus frequency


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    PDF CY7C1304V25 CY7C1304V25

    81c78

    Abstract: 7C291 5962-8515505RX 27PC256-12 PAL164A 8464C 5C6408 72018 39C10B MACH110 cross reference
    Text: Product Line Cross Reference CYPRESS 2147-35C 2147-45C 2147-45C 2147-45M+ 2147-55C 2147-55M 2148-35C 2148-35C 2148-35M 2148-45C 2148-45C 2148-45M 2148-45M+ 2148-55C 2148-55C 2148-55M 2149-35C 2149-35C 2149-35M 2149-45C 2149-45M 2149-45M 2149-55C 2149-55C 2149-55M


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    PDF 2147-35C 2147-45C 2147-45M+ 2147-55C 2147-55M 2148-35C 2148-35M 2148-45C 81c78 7C291 5962-8515505RX 27PC256-12 PAL164A 8464C 5C6408 72018 39C10B MACH110 cross reference

    Untitled

    Abstract: No abstract text available
    Text: 7C1302V25 9-Mb Pipelined SRAM with QDR Architecture Features Functional Description • • Separate Independent Read and Write Data Ports — Supports concurrent transactions • 167-MHz Clock for high bandwidth — 2.5 ns Clock-to-Valid access time


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    PDF CY7C1302V25 167-MHz CY7C1302V25

    CY7C130

    Abstract: CY7C131 CY7C140 CY7C141
    Text: 7C130, 7C130A CY7C131, CY7C131A 1 K x 8 Dual-Port Static RAM 1 K × 8 Dual-Port Static RAM Features Functional Description • True dual-ported memory cells, which allow simultaneous reads of the same memory location ■ 1 K × 8 organization ■ 0.65 micron CMOS for optimum speed and power


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    PDF CY7C130, CY7C130A CY7C131, CY7C131A CY7C130/130A/CY7C131/131A CY7C140/CY7C141 CY7C130/130A/CY7C131/131A; 48-pin CY7C13ication CY7C130 CY7C131 CY7C140 CY7C141

    96182

    Abstract: 9715 cy7c136
    Text: Cypress Semiconductor Qualification Report QTP# 97045/97154 VERSION 1.1 April, 1997 Dual Port SRAM - R28 Technology 7C130/131 1K x 8 Dual Port SRAM CY7C140/141 1K x 8 Dual Port SRAM CY7C132/136 2K x 8 Dual Port SRAM CY7C142/146 2K x 8 Dual Port SRAM Cypress Semiconductor


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    PDF CY7C130/131 CY7C140/141 CY7C132/136 CY7C142/146 CY7C13 /CY7C14* CY7C136 52-Lead CY7C025-JC CY7C025-AC 96182 9715 cy7c136

    Untitled

    Abstract: No abstract text available
    Text: 7C130 1 K x 8 Dual-Port Static RAM 1 K × 8 Dual-Port Static RAM Features Functional Description • True dual-ported memory cells, which allow simultaneous reads of the same memory location ■ 1 K × 8 organization ■ 0.65 micron CMOS for optimum speed and power


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    PDF CY7C130 CY7C130

    CY7C130

    Abstract: CY7C131 CY7C140 CY7C141
    Text: 7C130/CY7C131 CY7C140/CY7C141 1K x 8 Dual-Port Static RAM Features Functional Description • True Dual-Ported memory cells which allow simultaneous reads of the same memory location • 1K x 8 organization • 0.65-micron CMOS for optimum speed/power • High-speed access: 15 ns


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    PDF CY7C130/CY7C131 CY7C140/CY7C141 65-micron CY7C130/CY7C131 CY7C130/CY7C131; 48-pin CY7C130/140) 52-pin CY7C130 CY7C131 CY7C140 CY7C141

    CY7C1304V25

    Abstract: No abstract text available
    Text: 5 7C1304V25 Advanced Information 9-Mb Pipelined SRAM with QDR Architecture Features Functional Description • Separate Independent Read and Write Data Ports — Supports concurrent transactions • 167 MHz Clock for High Bandwidth — 2.5 ns Clock-to-Valid access time


    Original
    PDF CY7C1304V25 CY7C1304V25

    CY7C136E

    Abstract: CY7C131AE-15JXI CY7C136AE-55NXI
    Text: CY7C131E, CY7C131AE CY7C136E, CY7C136AE 1 K / 2 K x 8 Dual-port Static RAM 1 K / 2 K × 8 Dual-port Static RAM Features Functional Description • True dual-ported memory cells, which allow simultaneous reads of the same memory location ■ 1 K / 2 K × 8 organization


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    PDF CY7C131E, CY7C131AE CY7C136E, CY7C136AE CY7C131E CY7C136E CY7C136AE CY7C131AE-15JXI CY7C136AE-55NXI

    C1307

    Abstract: cY7c131 I CY7C130 CY7C131 CY7C140 CY7C141 C130-15 C1303 C13017
    Text: fax id: 5200 1CY 7C14 0 7C130/CY7C131 CY7C140/CY7C141 1K x 8 Dual-Port Static Ram Features Functional Description • True Dual-Ported memory cells which allow simultaneous reads of the same memory location • 1K x 8 organization • 0.65-micron CMOS for optimum speed/power


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    PDF CY7C130/CY7C131 CY7C140/CY7C141 65-micron CY7C130/CY7C131 CY7C130/CY7C131; 48-pin CY7C130/140) 52-pin C1307 cY7c131 I CY7C130 CY7C131 CY7C140 CY7C141 C130-15 C1303 C13017

    7C130

    Abstract: L1314
    Text: 7C130/CY7C131 CY7C140/CY7C141 _ 1024 x 8 Dual-Port Static RAM aT ^ p -¿r CYPRESS ^ SEMICONDUCTOR E ach p o rt has independent control pins; chip enable C E , w rite enable (RyW), and output The CY 7C130/CY7C131/CY7C140/ enable (O E ). TVvo flags are p rovided on each


    OCR Scan
    PDF CY7C130/CY7C131 CY7C140/ CY7C141 CY7C130/ CY7C131; CY7C140/CY7C141 7C130/CY7C131/CY7C140/ CY7C14 7C130 L1314

    cy7c131-55nc

    Abstract: ZT12 CY7C130 CY7C131 CY7C140 CY7C141 IDT7130 IDT7140
    Text: 7C130/CY7C131 CY7C140/CY7C141 W CYPRESS Features • 0.8-micron CMOS for optimum speed/power • Automatic power-down • TTL compatible • Capable o f withstanding greater than 2001V electrostatic discharge • Fully asynchronous operation • Master 7C130/CY7C131 easily ex­


    OCR Scan
    PDF CY7C130/CY7C131 CY7C140/CY7C141 CY7C140/ CY7C141 CY7C130/ CY7C131; IDT7130 IDT7140 cy7c131-55nc ZT12 CY7C130 CY7C131 CY7C140 CY7C141 IDT7140

    ebe switches

    Abstract: CY7C130 CY7C131 CY7C140 CY7C141 7CJ41-25 7CI40-35
    Text: CYPRESS SEMICONDUCTOR 00 0 3 4 2 1 EbE D 5 • 7C130/CY7C131 CY7C140/CY7C141 -Z Z A Z . o y n p rrQ C 1024 x 8 Dual-Port Static RAM SEMICONDUCTOR Features Functional Description • 0,8-micron CMOS for optimum speed/power • Automatic power-down • TTL-compatible


    OCR Scan
    PDF CY7C130/CY7C131 CY7C140/CY7C141 20O1V CY7C140/ CY7C141 CY7C130/ CY7C131; CY7C130/CY7C131/CY7C140/ ebe switches CY7C130 CY7C131 CY7C140 CY7C141 7CJ41-25 7CI40-35

    Untitled

    Abstract: No abstract text available
    Text: 7C130/CY7C131 CY7C140/CY7C141 CYPRESS SEMICONDUCTOR Features Functional Description • 0.8-micron CMOS for optimum speed/power • Automatic power-down • TTL compatible • Capable of withstanding greater than 2001V electrostatic discharge • Fully asynchronous operation


    OCR Scan
    PDF CY7C130/CY7C131 CY7C140/CY7C141 CY7C130/CY7C131 CY7C140/ CY7C141 CY7C130/ CY7C131; CY7C130/CY 7C131/CY7C140/

    Untitled

    Abstract: No abstract text available
    Text: fax id: 5200 7C130/CY7C131 CY7C140/CY7C141 W CYPRESS 1K x 8 Dual-Port Static Ram Features Functional Description True Dual-Ported memory cells which allow simulta­ neous reads of the same memory location 1K x 8 organization 0.65-micron CMOS for optimum speed/power


    OCR Scan
    PDF 130/C 140/C 65-micron CY7C130/CY7C131 CY7C140/CY7C141 CY7C130/CY7C131; 48-pin CY7C130/140) 52-pin

    Untitled

    Abstract: No abstract text available
    Text: 7C130/CY7C131 _ CY7C140/CY7C141 = SEMICONDUCTOR 1024 x 8 D ual-Port Static R A M Features Functional Description • 0.8-micron CMOS for optimum speed/power T he CY 7C 130/CY7C13 L/CY7C140/ CY7C141 arc high-speed C M O S IK by 8 dual-port static RA M s. Two ports are pro­


    OCR Scan
    PDF CY7C130/CY7C131 CY7C140/CY7C141 CY7C130/CY7CI31 CY7C140/ CY7C141 CY7C130/ CY7C131; CY7CI40/CY7C141 130/CY7C13 L/CY7C140/