MSG70 Search Results

ZL50011QCG1

Abstract: GR-1244-CORE MS-026 ZL50011
Contextual Info: ZL50011 Flexible 512 Channel DX with on-chip DPLL Data Sheet Features • March 2006 512 channel x 512 channel non-blocking switch at 2.048 Mbps, 4.096 Mbps or 8.192 Mbps operation Ordering Information 160 Pin LQFP Trays 144 Ball LBGA Trays 160 Pin LQFP* Trays, Bake & Drypack

ZL50010

Abstract: TFR1M GR-1244-CORE MS-026
Contextual Info: ZL50010 Flexible 512-ch DX with Enhanced DPLL Data Sheet Features VDD ZL50010/QCC ZL50010/GDC • • • • • • • • RESET Data Memory P/S Converter Output HiZ Control Connection Memory Microprocessor Interface and DPLL OSC Output Timing STo0-15 STOHZ0-15

MSM9225B

Abstract: MSM9225BGA M3MCR PCA82C250 QFP44-P-910-0 IDB25
Contextual Info: FEUL9225B-05 MSM9225B User’s Manual CAN Controller Area Network Controller Issue Date: July 1, 2002 NOTICE 1. The information contained herein can change without notice owing to product and/or technical improvements. Before using the product, please make sure that the information being referred to is up-to-date.

GR-1244-CORE

Abstract: MS-026 ZL50011 11CH marking
Contextual Info: ZL50011 Flexible 512 Channel DX with on-chip DPLL Data Sheet Features July 2004 • 512 channel x 512 channel non-blocking switch at 2.048 Mbps, 4.096 Mbps or 8.192 Mbps operation • Rate conversion between the ST-BUS inputs and ST-BUS outputs • Integrated Digital Phase-Locked Loop DPLL

MSG75

Abstract: IDB20 MSG61 cstcv16m0x51q GM0B MSG24 MSG70 1DLC2 2-34TEC TSEG13TSEG12TSEG11
Contextual Info: 1 FJUL9225B-04 MSM9225B ユーザーズマニュアル CAN（ CAN（Controller Area Network）コントローラ Network）コントローラ 第 4 版 2001 年 7 月作成 ご注意 1. 本書に記載された内容は製品改善及び技術改良等により将来予告なしに変更することがあります。したがって、

BC1211

Contextual Info: ZL50012 Flexible 512-ch Digital Switch Data Sheet Features July 2005 • 512 channel x 512 channel non-blocking switch at 2.048 Mb/s, 4.096 Mb/s or 8.192 Mb/s operation • Rate conversion between the ST-BUS inputs and ST-BUS outputs • Per-stream ST-BUS input with data rate selection

MSM9225B

Abstract: MSG20 MSG75 9225B FJUL9225B-02 MSM9225 MSM9225BGA PCA82C250 QFP44-P-910-0 msg66
Contextual Info: 1 FJUL9225B-02 ＭＳＭ9225B ＭＳＭ ユーザーズマニュアル CAN（ CAN（Controller Area Network）コントローラ Network）コントローラ 第 2 版 2000 年 8 月作成 ご注意 1. 本書に記載された内容は製品改善及び技術改良等により将来予告なしに変更することがあります。したがって、

chn 537

Abstract: I2S bus specification AVS service manual circuits CHN 65 ring COUNTER ADSP-21065L CB15S E22/6/BC635/637/639/pdf/pdf/buy/chn 537
Contextual Info: &21752/$1'67$786 5(*,67(56 Figure E-0. Table E-0. Listing E-0. This appendix lists and describes the bit definitions for the processor’s control and status registers. Some of the control and status registers are located in the processor’s core. These registers are called system registers.

MSM9225B

Abstract: MSG24 M3MCR MSM9225 MSM9225BGA-2K PCA82C250 QFP44-P-910-0 M5MS msg66 MSG20
Contextual Info: 1 FEUL9225B-04 MSM9225B User’s Manual CAN Controller Area Network Controller Oki Electric Industry Co., Ltd. Ver. 4.0 July 2001 NOTICE 1. The information contained herein can change without notice owing to product and/or technical improvements. Before using the

GR-1244-CORE

Abstract: MS-026 ZL50010
Contextual Info: ZL50010 Flexible 512 Channel DX with Enhanced DPLL Data Sheet Features VDD Per-stream output channel and output bit delay programming with fractional bit advancement Multiple frame pulse outputs and reference clock outputs Per-channel constant throughput delay

ZL50010QCG1

Abstract: GR-1244-CORE MS-026 ZL50010 32CH1
Contextual Info: ZL50010 Flexible 512 Channel DX with Enhanced DPLL Data Sheet Features VDD • • • • • • • • RESET Data Memory P/S Converter Output HiZ Control Connection Memory Microprocessor Interface and DPLL OSC Output Timing STo0-15 STOHZ0-15 FPo0 CKo0

MS-026

Abstract: ZL50012
Contextual Info: ZL50012 Flexible 512-ch Digital Switch Data Sheet Features July 2004 • 512 channel x 512 channel non-blocking switch at 2.048 Mb/s, 4.096 Mb/s or 8.192 Mb/s operation • Rate conversion between the ST-BUS inputs and ST-BUS outputs • Per-stream ST-BUS input with data rate selection

GR-1244-CORE

Abstract: MS-026 ZL50010 TFPW0
Contextual Info: ZL50010 Flexible 512 Channel DX with Enhanced DPLL Data Sheet Features VDD Per-stream output channel and output bit delay programming with fractional bit advancement Multiple frame pulse outputs and reference clock outputs Per-channel constant throughput delay

Contextual Info: ZL50011 Flexible 512 Channel DX with on-chip DPLL Data Sheet Features July 2005 • 512 channel x 512 channel non-blocking switch at 2.048 Mbps, 4.096 Mbps or 8.192 Mbps operation • Rate conversion between the ST-BUS inputs and ST-BUS outputs • Integrated Digital Phase-Locked Loop DPLL

FOX 20.000 MHZ

Abstract: LMT 324 slv ca2 GR-1244-CORE MS-026 ZL50010 STO14 tfk8k
Contextual Info: ZL50010 Flexible 512 Channel DX with Enhanced DPLL Data Sheet Features VDD Per-stream output channel and output bit delay programming with fractional bit advancement Multiple frame pulse outputs and reference clock outputs Per-channel constant throughput delay

VD0412HBGW

Abstract: MSA70 VD1212 0412M PITO
Contextual Info: ASSMANN Ordering Information Electronic C om ponen ts VD Motor VA = AC, 230 V VD = DC, 12 V Frame size: 02= 04 = 05= 06= 08 = 09= 12 = 25 x 25 40 x 40 52 x 52 60 x 60 80 x 80 92 x 92 120x 120 Voltages: 12= 12 V DC 23 = 230 V AC Speed: L = Low M = Medium H = High

CHN b42

Abstract: chn 743 pin of chn 743 chn 529 CHN 524 chn 729 CHN 849 CHN 616 CHN 847 RYM 17-18
Contextual Info: ADSP-21065L SHARC DSP Technical Reference Revision 2.0, July 2003 Part Number 82-001903-01 Analog Devices, Inc. One Technology Way Norwood, Mass. 02062-9106 a Copyright Information 2003 Analog Devices, Inc., ALL RIGHTS RESERVED. This document may not be reproduced in any form without prior, express written consent

IDB20

Contextual Info: FEUL9225B-05 MSM9225B User’s Manual CAN Controller Area Network Controller Issue Date: July 1, 2002 MSM9225B User’s Manual Contents Table of Contents Chapter 1 1.1 1.2 1.3 1.4 1.5 1.6 Overview Overview .1-1

GM76C256all

Abstract: 16M-DRAM LT-860 GM23C400 GM76C28A GM23C810QA-12 LR-80 BFW12 GM23C8001 GM23C410
Contextual Info: FUNCTION GUIDE DRAM Capacity 1MBit Org 1W0 Type No 4Wt1 1Mk4 Current mA Power Supply Feature Package (m il) Avail 18DIP(300) NOW tCAC tA A Active S/B GM71C1000B/BJ/BZ-60 GM71C10008/BJ/BZ-70 GM71C 10OÛB/BJ/BZ-ÔO 60 70 80 20 20 25 30 35 40 90 eo 70 1 GM71C10006UBLJ/BLZ-60

GR-1244-CORE

Abstract: MS-026 ZL50011
Contextual Info: ZL50011 Flexible 512-ch DX with on-chip DPLL Data Sheet Features VDD • • • Applications • • • • • Small and medium digital switching platforms Access Servers Time Division Multiplexers Computer Telephony Integration Digital Loop Carriers VSS

ZL50012QCG1

Abstract: MS-026 ZL50012 STO10
Contextual Info: ZL50012 Flexible 512-ch Digital Switch Data Sheet Features • April 2006 512 channel x 512 channel non-blocking switch at 2.048 Mb/s, 4.096 Mb/s or 8.192 Mb/s operation • Rate conversion between the ST-BUS inputs and ST-BUS outputs • Per-stream ST-BUS input with data rate selection

32.768Mhz oscillator

Abstract: FOX 20.000 MHZ GR-1244-CORE MS-026 ZL50011 tfk8
Contextual Info: ZL50011 Flexible 512 Channel DX with on-chip DPLL Data Sheet Features December 2003 • 512 channel x 512 channel non-blocking switch at 2.048 Mbps, 4.096 Mbps or 8.192 Mbps operation • Rate conversion between the ST-BUS inputs and ST-BUS outputs • Integrated Digital Phase-Locked Loop DPLL

msg4

Contextual Info: 1 FEUL9225B-03 MSM9225B User’s Manual CAN Controller Area Network Controller Oki Electric Industry Co., Ltd. Ver. 3.0 February 2001 NOTICE 1. The information contained herein can change without notice owing to product and/or technical improvements. Before using the

Contextual Info: ZL50011 Flexible 512 Channel DX with on-chip DPLL Data Sheet Features • September 2011 512 channel x 512 channel non-blocking switch at 2.048 Mbps, 4.096 Mbps or 8.192 Mbps operation Ordering Information ZL50011/GDC 144 Ball LBGA Trays ZL50011QCG1 160 Pin LQFP* Trays, Bake & Drypack