GR-1244-CORE
Abstract: ZL50015 ZL50015GAC ZL50015QCC ZL50015QCC1
Text: ZL50015 Enhanced 1 K Digital Switch with Stratum 4E DPLL Data Sheet Features • January 2006 1024 channel x 1024 channel non-blocking digital Time Division Multiplex TDM switch at 4.096, 8.192 and 16.384 Mbps or using a combination of ports running at 2.048, 4.096, 8.192 and
|
Original
|
ZL50015
ZL50015GAC
ZL50015QCC
ZL50015QCC1
ZL50015GAG2
GR-1244-CORE
ZL50015
ZL50015GAC
ZL50015QCC
ZL50015QCC1
|
PDF
|
ZL50011QCG1
Abstract: GR-1244-CORE MS-026 ZL50011
Text: ZL50011 Flexible 512 Channel DX with on-chip DPLL Data Sheet Features • March 2006 512 channel x 512 channel non-blocking switch at 2.048 Mbps, 4.096 Mbps or 8.192 Mbps operation Ordering Information 160 Pin LQFP Trays 144 Ball LBGA Trays 160 Pin LQFP* Trays, Bake & Drypack
|
Original
|
ZL50011
ZL50011/QCC
ZL50011/GDC
ZL50011QCG1
ZL50011GDG2
GR-1244-CORE
ZL50011QCG1
MS-026
ZL50011
|
PDF
|
ZL50010
Abstract: TFR1M GR-1244-CORE MS-026
Text: ZL50010 Flexible 512-ch DX with Enhanced DPLL Data Sheet Features VDD ZL50010/QCC ZL50010/GDC • • • • • • • • RESET Data Memory P/S Converter Output HiZ Control Connection Memory Microprocessor Interface and DPLL OSC Output Timing STo0-15 STOHZ0-15
|
Original
|
ZL50010
512-ch
STi0-15
ZL50010/QCC
ZL50010/GDC
IEEE-1149
ZL50010
TFR1M
GR-1244-CORE
MS-026
|
PDF
|
Untitled
Abstract: No abstract text available
Text: ZL50019 Enhanced 2 K Digital Switch with Stratum 4E DPLL Data Sheet Features September 2011 • 2048 channel x 2048 channel non-blocking digital Time Division Multiplex TDM switch at 8.192 and 16.384 Mbps or using a combination of ports running at 2.048, 4.096, 8.192 and 16.384 Mbps
|
Original
|
ZL50019
GR-1244-CORE
ZL50019GAC
ZL50019QCG1
ZL50019GAG2
|
PDF
|
GR-1244-CORE
Abstract: ZL50019 ZL50019GAC ZL50019QCC
Text: ZL50019 Enhanced 2 K Digital Switch with Stratum 4E DPLL Data Sheet Features November 2006 • 2048 channel x 2048 channel non-blocking digital Time Division Multiplex TDM switch at 8.192 and 16.384 Mbps or using a combination of ports running at 2.048, 4.096, 8.192 and 16.384 Mbps
|
Original
|
ZL50019
GR-1244-CORE
ZL50019
ZL50019GAC
ZL50019QCC
|
PDF
|
GR-1244-CORE
Abstract: MS-026 ZL50011 11CH marking
Text: ZL50011 Flexible 512 Channel DX with on-chip DPLL Data Sheet Features July 2004 • 512 channel x 512 channel non-blocking switch at 2.048 Mbps, 4.096 Mbps or 8.192 Mbps operation • Rate conversion between the ST-BUS inputs and ST-BUS outputs • Integrated Digital Phase-Locked Loop DPLL
|
Original
|
ZL50011
GR-1244-CORE
MS-026
ZL50011
11CH marking
|
PDF
|
GR-1244-CORE
Abstract: ZL50018 ZL50018GAC ZL50018QCC 99 mfu
Text: ZL50018 2 K Digital Switch with Enhanced Stratum 3 DPLL Data Sheet Features 2048 channel x 2048 channel non-blocking digital Time Division Multiplex TDM switch at 8.192 and 16.384 Mbps or using a combination of ports running at 2.048, 4.096, 8.192 and/or
|
Original
|
ZL50018
GR-1244-CORE
ZL50018GAC
256-ball
ZL50018QCC
256-lead
ZL50018
99 mfu
|
PDF
|
ZL50020
Abstract: ZL50020GAC ZL50020QCC
Text: ZL50020 Enhanced 2 K Digital Switch Data Sheet Features • October 2004 2048 channel x 2048 channel non-blocking digital Time Division Multiplex TDM switch at 8.192 Mbps and 16.384 Mbps or using a combination of ports running at 2.048, 4.096, 8.192 and 16.384 Mbps
|
Original
|
ZL50020
ZL50020GAC
256-ball
ZL50020QCC
256-lead
ZL50020
|
PDF
|
ZL50016
Abstract: ZL50016GAC ZL50016QCC
Text: ZL50016 Enhanced 1 K Digital Switch Data Sheet Features 1024 channel x 1024 channel non-blocking digital Time Division Multiplex TDM switch at 4.096 Mbps, 8.192 Mbps and 16.384 Mbps or using a combination of ports running at 2.048 Mbps, 4.096 Mbps, 8.192 Mbps and
|
Original
|
ZL50016
ZL50016GAC
256-ball
ZL50016QCC
256-lead
ZL50016
|
PDF
|
ZL50018
Abstract: GR-1244-CORE ZL50018GAC ZL50018QCC MFU 78
Text: ZL50018 2 K Digital Switch with Enhanced Stratum 3 DPLL Data Sheet Features November 2006 • 2048 channel x 2048 channel non-blocking digital Time Division Multiplex TDM switch at 8.192 and 16.384 Mbps or using a combination of ports running at 2.048, 4.096, 8.192 and/or
|
Original
|
ZL50018
GR-1244-CORE
ZL50018GAC
ZL50018QCC
ZL50018QCG1
ZL50018GAG2
ZL50018
ZL50018GAC
ZL50018QCC
MFU 78
|
PDF
|
Untitled
Abstract: No abstract text available
Text: ZL50023 Enhanced 4 K Digital Switch Data Sheet Features • February 2004 4096 channel x 4096 channel non-blocking digital Time Division Multiplex TDM switch at 8.192 Mbps and 16.384 Mbps or using a combination of ports running at 2.048 Mbps, 4.096 Mbps, 8.192 Mbps and 16.384 Mbps
|
Original
|
ZL50023
|
PDF
|
Untitled
Abstract: No abstract text available
Text: ZL50016 Enhanced 1 K Digital Switch Data Sheet Features 1024 channel x 1024 channel non-blocking digital Time Division Multiplex TDM switch at 4.096 Mbps, 8.192 Mbps and 16.384 Mbps or using a combination of ports running at 2.048 Mbps, 4.096 Mbps, 8.192 Mbps and
|
Original
|
ZL50016
ZL50016GAC
|
PDF
|
Untitled
Abstract: No abstract text available
Text: ZL50020 Enhanced 2 K Digital Switch Data Sheet Features • • January 2006 2048 channel x 2048 channel non-blocking digital Time Division Multiplex TDM switch at 8.192 Mbps and 16.384 Mbps or using a combination of ports running at 2.048, 4.096, 8.192 and 16.384 Mbps
|
Original
|
ZL50020
|
PDF
|
Untitled
Abstract: No abstract text available
Text: ZL50016 Enhanced 1 K Digital Switch Data Sheet Features 1024 channel x 1024 channel non-blocking digital Time Division Multiplex TDM switch at 4.096 Mbps, 8.192 Mbps and 16.384 Mbps or using a combination of ports running at 2.048 Mbps, 4.096 Mbps, 8.192 Mbps and
|
Original
|
ZL50016
|
PDF
|
|
|
Untitled
Abstract: No abstract text available
Text: ZL50022 Enhanced 4 K Digital Switch with Stratum 4E DPLL Data Sheet Features 4096 channel x 4096 channel non-blocking digital Time Division Multiplex TDM switch at 8.192 Mbps and 16.384 Mbps or using a combination of ports running at 2.048, 4.096, 8.192 and 16.384 Mbps
|
Original
|
ZL50022
GR-1244-CORE
ZL50022GAC
256-ball
ZL50022QCC
256-lead
|
PDF
|
Untitled
Abstract: No abstract text available
Text: ZL50015 Enhanced 1 K Digital Switch with Stratum 4E DPLL Data Sheet Features 1024 channel x 1024 channel non-blocking digital Time Division Multiplex TDM switch at 4.096, 8.192 and 16.384 Mbps or using a combination of ports running at 2.048, 4.096, 8.192 and
|
Original
|
ZL50015
GR-1244-CORE
|
PDF
|
dpm001
Abstract: PMS01
Text: ZL50019 Enhanced 2 K Digital Switch with Stratum 4E DPLL Data Sheet Features • • 2048 channel x 2048 channel non-blocking digital Time Division Multiplex TDM switch at 8.192 and 16.384 Mbps or using a combination of ports running at 2.048, 4.096, 8.192 and 16.384 Mbps
|
Original
|
ZL50019
GR-1244-CORE
ZL50019GAC
ZL50019QCC
dpm001
PMS01
|
PDF
|
ZL50020
Abstract: ZL50020GAC ZL50020QCC ZL50020QCG1
Text: ZL50020 Enhanced 2 K Digital Switch Data Sheet Features • November 2006 2048 channel x 2048 channel non-blocking digital Time Division Multiplex TDM switch at 8.192 Mbps and 16.384 Mbps or using a combination of ports running at 2.048, 4.096, 8.192 and 16.384 Mbps
|
Original
|
ZL50020
ZL50020GAC
ZL50020QCC
ZL50020QCG1
ZL50020GAG2
ZL50020
ZL50020GAC
ZL50020QCC
ZL50020QCG1
|
PDF
|
Untitled
Abstract: No abstract text available
Text: ZL50015 Enhanced 1 K Digital Switch with Stratum 4E DPLL Data Sheet Features • • 1024 channel x 1024 channel non-blocking digital Time Division Multiplex TDM switch at 4.096, 8.192 and 16.384 Mbps or using a combination of ports running at 2.048, 4.096, 8.192 and
|
Original
|
ZL50015
ZL50015GAC
ZL50015QCC1
ZL50015GAG2
GR-1244-CORE
|
PDF
|
GR-1244-CORE
Abstract: MS-026 ZL50010
Text: ZL50010 Flexible 512 Channel DX with Enhanced DPLL Data Sheet Features VDD Per-stream output channel and output bit delay programming with fractional bit advancement Multiple frame pulse outputs and reference clock outputs Per-channel constant throughput delay
|
Original
|
ZL50010
STi0-15
ZL50010/QCC
ZL50010/GDC
IEEE-1149
GR-1244-CORE
MS-026
ZL50010
|
PDF
|
ZL50010QCG1
Abstract: GR-1244-CORE MS-026 ZL50010 32CH1
Text: ZL50010 Flexible 512 Channel DX with Enhanced DPLL Data Sheet Features VDD • • • • • • • • RESET Data Memory P/S Converter Output HiZ Control Connection Memory Microprocessor Interface and DPLL OSC Output Timing STo0-15 STOHZ0-15 FPo0 CKo0
|
Original
|
ZL50010
STi0-15
ZL50010/QCC
ZL50010/GDC
ZL50010QCG1
ZL50010GDG2
ZL50010QCG1
GR-1244-CORE
MS-026
ZL50010
32CH1
|
PDF
|
GR-1244-CORE
Abstract: ZL50021 ZL50021GAC ZL50021QCC
Text: ZL50021 Enhanced 4 K Digital Switch with Stratum 3 DPLL Data Sheet Features 4096-channel x 4096-channel non-blocking digital Time Division Multiplex TDM switch at 8.192 and 16.384 Mbps or using a combination of ports running at 2.048, 4.096, 8.192 and/or
|
Original
|
ZL50021
4096-channel
GR-1244-CORE
ZL50021GAC
256-ball
ZL50021QCC
256-lead
ZL50021
|
PDF
|
MS-026
Abstract: ZL50012
Text: ZL50012 Flexible 512-ch Digital Switch Data Sheet Features July 2004 • 512 channel x 512 channel non-blocking switch at 2.048 Mb/s, 4.096 Mb/s or 8.192 Mb/s operation • Rate conversion between the ST-BUS inputs and ST-BUS outputs • Per-stream ST-BUS input with data rate selection
|
Original
|
ZL50012
512-ch
ZL50012/QCC
ZL50012/GDC
MS-026
ZL50012
|
PDF
|
GR-1244-CORE
Abstract: MS-026 ZL50010 TFPW0
Text: ZL50010 Flexible 512 Channel DX with Enhanced DPLL Data Sheet Features VDD Per-stream output channel and output bit delay programming with fractional bit advancement Multiple frame pulse outputs and reference clock outputs Per-channel constant throughput delay
|
Original
|
ZL50010
STi0-15
ZL50010/QCC
ZL50010/GDC
IEEE-1149
GR-1244-CORE
MS-026
ZL50010
TFPW0
|
PDF
|
