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    LH521007 Search Results

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    LH521007 Price and Stock

    Sharp Microelectronics of the Americas LH521007AK-17

    Distributors Part Package Stock Lead Time Min Order Qty Price Buy
    Bristol Electronics LH521007AK-17 338 1
    • 1 $6.72
    • 10 $4.368
    • 100 $2.9118
    • 1000 $2.7552
    • 10000 $2.7552
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    Quest Components LH521007AK-17 270
    • 1 $9
    • 10 $9
    • 100 $4.2
    • 1000 $3.9
    • 10000 $3.9
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    LH521007AK-17 148
    • 1 $10.8
    • 10 $7.2
    • 100 $6.66
    • 1000 $6.66
    • 10000 $6.66
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    Not Specified LH521007AK-17

    Distributors Part Package Stock Lead Time Min Order Qty Price Buy
    Bristol Electronics LH521007AK-17 37
    • 1 -
    • 10 -
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    • 10000 -
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    Sharp Microelectronics of the Americas LH521007CK-20

    IC,SRAM,128KX8,CMOS,SOJ,32PIN,PLASTIC
    Distributors Part Package Stock Lead Time Min Order Qty Price Buy
    Quest Components LH521007CK-20 17,397
    • 1 $4.5
    • 10 $4.5
    • 100 $4.5
    • 1000 $4.5
    • 10000 $1.575
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    Sharp Microelectronics of the Americas LH521007AK-20

    STANDARD SRAM, 128KX8, 20NS, CMOS, PDSO32
    Distributors Part Package Stock Lead Time Min Order Qty Price Buy
    Quest Components LH521007AK-20 489
    • 1 $15
    • 10 $15
    • 100 $15
    • 1000 $7.5
    • 10000 $7.5
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    LH521007AK-20 6
    • 1 $15
    • 10 $7.5
    • 100 $7.5
    • 1000 $7.5
    • 10000 $7.5
    		Buy Now

    Sharp Microelectronics of the Americas LH521007BK-20

    Distributors Part Package Stock Lead Time Min Order Qty Price Buy
    Quest Components LH521007BK-20 8
    • 1 $13.7148
    • 10 $9.1432
    • 100 $9.1432
    • 1000 $9.1432
    • 10000 $9.1432
    		Buy Now

    LH521007 Datasheets (25)

    Part ECAD Model Manufacturer Description Curated Datasheet Type PDF
    LH521007AK-17 Sharp SRAM GP Single Port Original PDF
    LH521007AK-20 Sharp SRAM GP Single Port Original PDF
    LH521007AK-25 Sharp SRAM GP Single Port Original PDF
    LH521007BK-17 Sharp SRAM GP Single Port Original PDF
    LH521007BK-17L Sharp SRAM GP Single Port Original PDF
    LH521007BK-20 Sharp SRAM GP Single Port Original PDF
    LH521007BK-20L Sharp SRAM GP Single Port Original PDF
    LH521007BK-25 Sharp SRAM GP Single Port Original PDF
    LH521007BK-25L Sharp SRAM GP Single Port Original PDF
    LH521007BK-35 Sharp SRAM GP Single Port Original PDF
    LH521007BK-35L Sharp SRAM GP Single Port Original PDF
    LH521007BNK-17 Sharp SRAM GP Single Port Original PDF
    LH521007BNK-17L Sharp SRAM GP Single Port Original PDF
    LH521007BNK-20 Sharp SRAM GP Single Port Original PDF
    LH521007BNK-20L Sharp SRAM GP Single Port Original PDF
    LH521007BNK-25 Sharp SRAM GP Single Port Original PDF
    LH521007BNK-25L Sharp SRAM GP Single Port Original PDF
    LH521007BNK-35 Sharp SRAM GP Single Port Original PDF
    LH521007BNK-35L Sharp SRAM GP Single Port Original PDF
    LH521007CK-17 Sharp SRAM GP Single Port Original PDF

    LH521007 Datasheets Context Search

    Catalog Datasheet MFG & Type PDF Document Tags

    LH521007AK-25

    Abstract: lh521007ak 32-PIN
    Text: LH521007A FEATURES • Fast Access Times: 17/20/25 ns • Two Chip Enable Controls • Low-Power Standby When Deselected • TTL Compatible I/O • 5 V ±10% Supply • Fully-Static Operation • 2 V Data Retention • Package: 32-Pin, 400-mil SOJ FUNCTIONAL DESCRIPTION


    Original     		PDF LH521007A 32-Pin, 400-mil LH521007A 576-bit 32SOJ400A LH521007AK-25 lh521007ak 32-PIN

    32-PIN

    Abstract: No abstract text available
    Text: LH521007B FEATURES • Fast Access Times: 17/20/25/35 ns • Two Chip Enable Controls • Low Power Standby When Deselected • TTL Compatible I/O • 5 V ± 10% Supply • Fully Static Operation • 2 V Data Retention L Version • Packages: 32-Pin, 300-mil SOJ (Preliminary)


    Original     		PDF LH521007B 32-Pin, 300-mil 400-mil 32SOJ400 32-PIN

    32-PIN

    Abstract: SOJ32-P-300
    Text: LH521007C CMOS 128K x 8 Static RAM Data Sheet When both Chip Enables are active and W is inactive, a static Read will occur at the memory location specified by the address lines. G must be brought LOW to enable the outputs. Since the device is fully static in operation,


    Original     		PDF LH521007C 2613-banchi, J63428 SMT94021 32-PIN SOJ32-P-300

    SOJ32

    Abstract: 32-PIN SOJ32-P-300 LH521007ck
    Text: LH521007C CMOS 128K x 8 Static RAM Data Sheet When both Chip Enables are active and W is inactive, a static Read will occur at the memory location specified by the address lines. G must be brought LOW to enable the outputs. Since the device is fully static in operation,


    Original     		PDF LH521007C 2613-banchi, J63428 SMT94021 SOJ32 32-PIN SOJ32-P-300 LH521007ck

    MCS-96 Users guide

    Abstract: 80C296SA LED Sign Board Diagram 80c296 ApBUILDER 80296SA A517 intel asm96 mcs96 transistor a5171
    Text: 80296SA Evaluation Board Manual October, 1996 Order Number: 272947-001 satarget.bk : satitle.fm5 Page i Wednesday, October 23, 1996 5:46 PM 80296SA Evaluation Board Manual October 1996 satarget.bk : satitle.fm5 Page ii Wednesday, October 23, 1996 5:46 PM Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel’s Terms and Conditions of


    Original     		PDF 80296SA 80296SA EMC96SA MCS-96 Users guide 80C296SA LED Sign Board Diagram 80c296 ApBUILDER A517 intel asm96 mcs96 transistor a5171

    mn4117405

    Abstract: NN5118165 XL93LC46AP NN514265 MS6264L-10PC w24M257 NN514265A w24m257ak-15 HY62256ALP10 mhs p80c51
    Text: ISSI CROSS REFERENCE GUIDE Integrated Silicon Solution, Inc. ISSI ® Integrated Silicon Solution, Inc. CROSS REFERENCE GUIDE SRAM DRAM EEPROM EPROM MICROCONTROLLER JUNE 1999 Integrated Silicon Solution, Inc. CP005-1F 6/1/99 1 ISSI CROSS REFERENCE GUIDE


    Original     		PDF CP005-1F IS89C51 Z16C02 Z86E30 ZZ16C03 Z8036 Z8536 Z8038 Z5380 Z53C80 mn4117405 NN5118165 XL93LC46AP NN514265 MS6264L-10PC w24M257 NN514265A w24m257ak-15 HY62256ALP10 mhs p80c51

    UM61256AK-15

    Abstract: UM61256ak sram um61256ck-20 HY62256ALP10 XL93LC46AP w24m257 GVT7164D32Q-6 km62256blg-7 w24m257ak-15 UM61256
    Text: ISSI CROSS REFERENCE GUIDE Integrated Silicon Solution, Inc. ISSI ® Integrated Silicon Solution, Inc. CROSS REFERENCE GUIDE SRAM DRAM EEPROM EPROM FLASH MICROCONTROLLER SERIAL FLASH JULY 1998 Integrated Silicon Solution, Inc. CP005-1E 7/1/98 1 ISSI CROSS REFERENCE GUIDE


    Original     		PDF CP005-1E AS7C1024-12JC AS7C1024-12PC AS7C1024-12TJC AS7C1024-12TPC AS7C1024-15JC AS7C1024-15PC AS7C1024-15TJC AS7C1024-15TPC AS7C1024-20JC UM61256AK-15 UM61256ak sram um61256ck-20 HY62256ALP10 XL93LC46AP w24m257 GVT7164D32Q-6 km62256blg-7 w24m257ak-15 UM61256

    um61256ak-15

    Abstract: w24m257ak-15 um61256 um61256ck-20 um61256ak-12 km62256blg-7 KM68257Bp-20 W24M257AK HY6264ALP-10 w24M257
    Text: ISSI Integrated Silicon Solution, Inc. CROSS REFERENCE GUIDE SRAM/NVM Serial EEPROM EPROM FLASH Static RAM SEPTEMBER 1996 CROSS REFERENCE GUIDE E2PROM ATMEL ISSI MIL PACKAGE SYMBOL PC P SC G SC GR AT93C46-10PC AT93C46-10PC-2.7 AT93C46-10SC AT93C46-10SC-2.7


    Original     		PDF AT93C46-10PC AT93C46-10PC-2 AT93C46-10SC AT93C46-10SC-2 AT93C46R-10SC AT93C46R-10SC-2 AT93C46W-10SC AT93C46W-10SC-2 AT93C56-10PC AT93C56-10PC-2 um61256ak-15 w24m257ak-15 um61256 um61256ck-20 um61256ak-12 km62256blg-7 KM68257Bp-20 W24M257AK HY6264ALP-10 w24M257

    Spil polyimide system in package

    Abstract: B-629
    Text: SHARP LH521007C Data Sheet CMOS 128K X 8 Static RAM FEATURES When both Chip Enables are active and W is inactive, a static Read will occur at the memory location specified by the address lines. G must be brought LOW to enable the outputs. Since the device is fully static in operation,


    OCR Scan     		PDF 32-Pin, 300-mil 400-mil LH521007C 576-bit -65sC~ 2604C 1500G, LH521002CK Spil polyimide system in package B-629

    lh521007

    Abstract: No abstract text available
    Text: PRELIMINARY LH521007/ FEATURES • Fast Access Times: 20 725/35 ns • Two Chip Enable Controls • High Density 32-Pin, 400-mil SOJ • Low Power Standby When Deselected • TTL Compatible I/O • 5 V ± 10% Supply • Fully Static Operation • 2 V Data Retention


    OCR Scan     		PDF LH521007/ 32-Pin, 400-mil LH521007 SOJ32-P-400) LH521007K-25 lh521007

    DIP32-P-400

    Abstract: No abstract text available
    Text: PRELIMINARY LH521007 FEATURES • Fast Access Times: 20/25/35 ns • Two Chip Enable Controls • Low Power Standby When Deselected • TTL Compatible I/O • 5 V ± 10% Supply • Fully Static Operation • 2 V Data Retention • Packages: 32-Pin, 400-mil DIP


    OCR Scan     		PDF LH521007 32-Pin, 400-mil SOJ32-P-4001 DIP32-P-400

    Untitled

    Abstract: No abstract text available
    Text: SHARP LH521007C CMOS 128K x 8 Static RAM Data Sheet When both Chip Enables are active and W is inactive, a static Read will occur at the memory location specified by the address lines. G must be brought LOW to enable the outputs. Since the device is fully static in operation,


    OCR Scan     		PDF 32-Pin, 300-mil 400-mil LH521007C EME9300H 150mA LH521002QK 256Kx4) FRCRE002

    lh57257

    Abstract: IR2E31 IR2E01 IR2C07 IR2E27 IR2E24 IR2E19 IR2E31A IR3n06 IR2E02
    Text: Index Model No. ARM7D CPU Core Bi-CMOS 1 27 40,42 _ _ CMOS CMOS CMOS CMOS CMOS 4A 5A 8 A AH D ID1 Series ID2 Series 40,42 40.42 40,42 40,42 40 B ü.’1*"! 14,15 14 m IR2339 IR2403 IR2406 IR2406G IR2410 IR2411 IR2415 IR2419 IR2420 IR2422 IR2425 IR2429


    OCR Scan     		PDF IR2E201 IR2E24 IR2E27/A IR2E28 IR2E29 IR2E30 IR2E31/A IR2E32N9 IR2E34 IR2E41 lh57257 IR2E31 IR2E01 IR2C07 IR2E27 IR2E19 IR2E31A IR3n06 IR2E02

    Untitled

    Abstract: No abstract text available
    Text: MEMORIES * S tic RAMs Process C apacity Configuration Model No. A ccess tim e ns 70 80 90 100 120 LH5116 16k Full CMOS 64k 2k X 8 8k X 8 LH5116H f- Supply voltage : 5 V * 10% QpewBng tew ^raw » : ~ 40to85'C LH5116S j- Supply voltage : 3 V ± 10% LH5164A


    OCR Scan     		PDF LH5116 LH5116H LH5116S LH5164A LH5164AH 40to85 LH5164AV LH51V256H LH5268A LH52256A

    Untitled

    Abstract: No abstract text available
    Text: CMOS 128K x 8 S tatic RAM FEATURES • Fast Access Times: 17/20/25 ns • Two Chip Enable Controls • Low-Power Standby When Deselected • TTL Compatible I/O • 5 V ±10% Supply • Fully-Static Operation • 2 V Data Retention • Package: 32-Pin, 400-mil SOJ


    OCR Scan     		PDF 32-Pin, 400-mil LH521007A 576-bit 32-PIN 521007B-1

    LQ070T5BG01

    Abstract: LM24P20 LM162KS1 BSCR86L00 IR2C07 LM5Q31 IR3Y29B BSCU86L60 lq6bw lq6bw506
    Text: INDEX 1 0 4 - 1 0 9 _ DC_ GL1PR112.69 GL3KG63. 66 GL5EG41.66 1 0 4 - n 0 5 O o c .113 DC1B1CP. 100 GL1PR135.69 GL3KG8. 66


    OCR Scan     		PDF 109-n GL1PR112. GL1PR135. GL1PR136. GL1PR211. GL1PR212. GL3KG63. GL3P201. GL3P202. GL3P305. LQ070T5BG01 LM24P20 LM162KS1 BSCR86L00 IR2C07 LM5Q31 IR3Y29B BSCU86L60 lq6bw lq6bw506

    organizational structure samsung

    Abstract: NMS256X8 MICRON Cross Reference NMS256 256K RAM HM62256 MK6264 51256SL TC5565 "cross reference" MN44256 M5M5256
    Text: Static RAM Cross Reference STATIC RAM CROSS REFERENCE ORGANIZATIONAL STRUCTURE 2K 2K X X 32K 8K X e w/CE, OE 8 W/CE1, CE2 X 8 Stow 8 Slow COMPETITIVE VENDOR SH ARP MODEL LH5116 LH5118 LH51256 LH5164A AMD Am9128 Harris CDM6116 Hitachi HM6116A Hyundai HY6116


    OCR Scan     		PDF LH5116 Am9128 CDM6116 HM6116A HY6116 HM6116 MS6516 SRM2016 MK6116 CXK5816 organizational structure samsung NMS256X8 MICRON Cross Reference NMS256 256K RAM HM62256 MK6264 51256SL TC5565 "cross reference" MN44256 M5M5256

    lh5168

    Abstract: No abstract text available
    Text: MEMORIES Static RAMs ★ Under development P ro ce ss C a p a c ity C o n fig u ra tio n Model No. A c c e s s tim e n s 70 80 90 100 120 LH5116 2k X 8 16k LH51116H Operating temperature : - 40 to 8 5 t IUUU "O LH5116S Supply voltage : 3 V±10% LH5168 Full


    OCR Scan     		PDF LH5116 LH51116H LH5116S LH5168 LH5168H LH5168V LH5168S LH5168SH LH5164AH 5164AV

    Untitled

    Abstract: No abstract text available
    Text: CMOS 128K x 8 Static RAM FEATURES • Fast Access Times: 20/25/35 ns • Two Chip Enable Controls • Low-Power Standby When Deselected • TTL Compatible I/O • 5 V ±10% Supply • Fully-Static Operation • 2 V Data Retention • Package: 32-Pin, 400-mil SOJ


    OCR Scan     		PDF 32-Pin, 400-mil LH521007A 576-bit LH521007A SQJ32-P-400) LH521007AK-25 400-mii

    5268A

    Abstract: 28-SOP LH521002AK-2S 28SOP LH52256CVN
    Text: MEMORIES S tatic RAMs Process Capacity Configuation words Xbits 2k 16k 8 X Access time Supply current ns) MAX. Cycle time Operating, Standby (ns) MIN. !mA) MAX. (mA) MAX. Model No. Supply Operating voltage temp. 0C) m i i LH 5116/NA/D-10 100 40 0.001 5 ± 10%


    OCR Scan     		PDF 5116/NA/D-10 LH5116H/HN/HD-10 LH5116SN LH5164A/AN-80L LH5164A /AT-10L 24DIP/24SOP/24SK-DIP 24SOP 28SOP/ 5268A 28-SOP LH521002AK-2S 28SOP LH52256CVN

    LH521007AK-20

    Abstract: No abstract text available
    Text: STATIC RAM ☆ New product ★ Under development STATIC RAMs ♦ Features • The product lineup includes a wide variety of bit configurations x4, x8, x l6 , x l8 , x32 . • High-speed synchronous devices for the secondary cache memory are available for use with low-voltage, lowpower CPUs idpal for portable equipment.


    OCR Scan     		PDF LH5116SN LH5164AVN/AVT LH5164AV3HN 24SOP 28S0P/28TS0P LH5268A/AN/AD-1 52256C -70LIÆ 710LL LH521007AK-20

    LHS168

    Abstract: LH52252A LH52252
    Text: V .J 1 íVt! Static RAMs ★Under development Process Capacity Model No. Configuration Access time ns 70 -I 16k 2k Package 90 100 120 LH5116 J— I. 24 24 24 LH5116H 3 -T 24 24 24 - Z ÏÏ-J 1 24 24 24 C E , C S c o n tro l Data retention current : 0.2 pAjMAXj j


    OCR Scan     		PDF LH5116 LH5116H LH5116S LH5117 LH511 LH5118 LH5118H LH52252A LH52253 LH521002A LHS168 LH52252

    IR2E27A

    Abstract: IR2C53 IR2E02 IR2E27 IR2E10 IR3N34 IR2E31A IR2E01 IR2C07 ir2e31
    Text: lndeX Model No. ARM7D CPU Core28,32,33 ARM7DM 28,33 CMOS CMOS CMOS CMOS 76 5A A F G 44 44 44 44 ID1 series ID2 series ID3 seríes ID21K064 ID21K128 ID21K256 ID21K512 ID21M010 ID21M015 ID21M020 ID21M040 ID22K256 ID22K512 ID22M010 ID22M020 ID22M040 ID22M080


    OCR Scan     		PDF Core28 IR2C24A/AN IR2C26 IR2C30/N IR2C32 IR2C33 IR2C34 IR2C36 IR2C38/N IR2C43 IR2E27A IR2C53 IR2E02 IR2E27 IR2E10 IR3N34 IR2E31A IR2E01 IR2C07 ir2e31

    Untitled

    Abstract: No abstract text available
    Text: CMOS 128K x 8 Static RAM FEATURES • Fast Access Times: 17/20/25/35 ns • Two Chip Enable Controls • Low Power Standby When Deselected • TTL Compatible I/O • 5 V ± 10% Supply • Fully Static Operation • 2 V Data Retention L Version • Packages:


    OCR Scan     		PDF 32-Pin, 300-mil 400-mil LH521007B 576-bit LH521007B 1007B