KM48S8030C Search Results
KM48S8030C Price and Stock
Samsung Semiconductor KM48S8030CT-GL |
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KM48S8030CT-GL | 39 |
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Samsung Semiconductor KM48S8030CT-G10IC,SDRAM,4X2MX8,CMOS,TSOP,54PIN,PLASTIC |
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KM48S8030CT-G10 | 128 |
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KM48S8030C Datasheets (8)
Part | ECAD Model | Manufacturer | Description | Curated | Datasheet Type | |
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KM48S8030C |
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2M x 8-Bit x 4 Banks Synchronous DRAM | Original | |||
KM48S8030CT-G/F10 |
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2M x 8-Bit x 4 Banks Synchronous DRAM | Original | |||
KM48S8030CT-G/F7 |
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2M x 8-Bit x 4 Banks Synchronous DRAM | Original | |||
KM48S8030CT-G/F8 |
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2M x 8-Bit x 4 Banks Synchronous DRAM | Original | |||
KM48S8030CT-G/FA |
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2M x 8-Bit x 4 Banks Synchronous DRAM | Original | |||
KM48S8030CT-G/FH |
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2M x 8-Bit x 4 Banks Synchronous DRAM | Original | |||
KM48S8030CT-G/FL |
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2M x 8-Bit x 4 Banks Synchronous DRAM | Original | |||
KM48S8030CT-GL |
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KM48S8030CT 2M x 8-Bit x 4 Banks Synchronous DRAM Organization = 8Mx8 Bank/ Interface = 4B/LVTTL Refresh = 4K/64ms Speed = 75,80,1H,1L,10 Package = 54TSOP2 Power = C,l Production Status = Eol Comments = - | Original |
KM48S8030C Datasheets Context Search
Catalog Datasheet | Type | Document Tags | |
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Contextual Info: Preliminary SDRAM R evision H istory R evision 1 M ay 1998 - ICC2 N va lu e (10m A) is cha ng ed to 12m A. Revision .2 (June 1998) - tSH (-10 binning) is revised. REV. 2 June '98 ELECTRONICS Preliminary |
OCR Scan |
KM48S8030C_ KM48S8030C KM48S8030C 10/AP | |
Contextual Info: Preliminary CMOS SDRAM KM48S8030C 2M x 8Bit x 4 Banks Synchronous DRAM FEATURES GENERAL DESCRIPTION • • • • The KM48S8030C is 67,108,864 bits synchronous high data rate Dynamic RAM organized as 4 x 2,097,152 words by 8 bits, fabricated with SAMSUNG'S high performance CMOS technol |
OCR Scan |
KM48S8030C KM48S8030C 10/AP | |
KM48S8030CContextual Info: KM48S8030C Preliminary CMOS SDRAM Revision History Revision 1 May 1998 - ICC2N value (10mA) is changed to 12mA. Revision .2 (June 1998) - tSH (-10 binning) is revised. REV. 2 June '98 Preliminary CMOS SDRAM KM48S8030C 2M x 8Bit x 4 Banks Synchronous DRAM |
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KM48S8030C KM48S8030C 10/AP | |
KM48S8030C
Abstract: KM48S803 PC133 1998
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KM48S8030C PC133 KM48S8030C A10/AP KM48S803 PC133 1998 | |
Contextual Info: KMM374S823CTS PC100 Unbuffered DIMM Revision History Revision 0.1 Mar. 24, 1999 - Changed "Detail C" in PCB Dimension. - Changed decoupling capacitance from two 0.1uF to one 0.1uF and one 0.33 uF. Rev.0.1 Mar 1999 KMM374S823CTS PC100 Unbuffered DIMM KMM374S823CTS SDRAM DIMM |
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KMM374S823CTS PC100 KMM374S823CTS 8Mx72 400mil 168-pin | |
KMM466S823CT2-F0Contextual Info: KMM466S823CT2 Preliminary 144pin SDRAM SODIMM Revision History Revision 2 August 1998 1. Correct DQ No. in Fuctional Block Diagram. Change DQ8 ~ DQ15 to DQ0 ~ DQ7. REV. 2 August 1998 Preliminary 144pin SDRAM SODIMM KMM466S823CT2 KMM466S823CT2 SDRAM SODIMM |
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KMM466S823CT2 144pin KMM466S823CT2 8Mx64 400mil 144-pin KMM466S823CT2-F0 | |
KMM377S823CT2-GH
Abstract: KMM377S823CT2-GL
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KMM377S823CT2 KMM377S823CT2 8Mx72 400mil 18-bits 24-pin 168pin 0022uF KMM377S823CT2-GH KMM377S823CT2-GL | |
KMM374S1623CT-GHContextual Info: KMM374S1623CT PC100 Unbuffered DIMM Revision History [ Rev. 1 ] March 23. 1999 Functional Block Diagram and Package dimension changed. Rev.1 Mar. 1999 KMM374S1623CT PC100 Unbuffered DIMM KMM374S1623CT SDRAM DIMM 16Mx72 SDRAM DIMM with ECC based on 8Mx8, 4Banks, 4K Refresh, 3.3V Synchronous DRAMs with SPD |
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KMM374S1623CT PC100 KMM374S1623CT 16Mx72 400mil 168-pin KMM374S1623CT-GH | |
KMM377S823CT3-GH
Abstract: KMM377S823CT3-GL
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KMM377S823CT3 KMM377S823CT3 8Mx72 400mil 18-bits 24-pin 168pin 0022uF KMM377S823CT3-GH KMM377S823CT3-GL | |
Contextual Info: Preliminary KMM466S823CT3_144pin SDRAM SODIMM Revision History Revision 2 August 1998 1. C orrect DQ No. in Fuctionai Block Diagram. Change DQ8 ~ DQ15 to DQO ~ DQ7. REV. 2 August 1998 ELECTROMCS Preliminary KMM466S823CT3_144pin SDRAM SODIMM |
OCR Scan |
KMM466S823CT3_ 144pin KMM466S823CT3 8Mx64 400mil 144-and | |
Contextual Info: KMM466S823CT2 Preliminary 144pin SDRAM SODIMM Revision History Revision 2 August 1998 1. C orrect DQ No. in Fuctionai Block Diagram. Change DQ8 ~ DQ15 to DQO ~ DQ7. REV. 2 August 1998 ELECTROMCS Preliminary 144pin SDRAM SODIMM KMM466S823CT2 KMM466S823CT2 SDRAM SODIMM |
OCR Scan |
KMM466S823CT2 144pin KMM466S823CT2 8Mx64 400mil 144-pin | |
Contextual Info: KMM377S823CT3 PC100 Registered DIMM Revision History Revision 0.1 May. 24, 1999 - Changed "Detail C" in PCB Dimension. Rev. 0.1 May. 1999 PC100 Registered DIMM KMM377S823CT3 KMM377S823CT3 SDRAM DIMM 8Mx72 SDRAM DIMM with PLL & Register based on 8Mx8, 4Banks 4K Ref., 3.3V Synchronous DRAMs with SPD |
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KMM377S823CT3 PC100 KMM377S823CT3 8Mx72 400mil 18-bits | |
KMM374S1623CT-GLContextual Info: KMM374S1623CT PC100 Unbuffered DIMM Revision History Revision 0.1 Mar. 23, 1999 - Changed "Detail C" in PCB Dimension. Rev.0.1 Mar. 1999 KMM374S1623CT PC100 Unbuffered DIMM KMM374S1623CT SDRAM DIMM 16Mx72 SDRAM DIMM with ECC based on 8Mx8, 4Banks, 4K Refresh, 3.3V Synchronous DRAMs with SPD |
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KMM374S1623CT PC100 KMM374S1623CT 16Mx72 400mil 168-pin KMM374S1623CT-GL | |
M374S823CTContextual Info: PC100 SDRAM MODULE KM M374S823CTS KMM374S823CTS SDRAM DIMM 8Mx72 SDRAM DIMM with ECC based on 8Mx8, 4Banks, 4K Refresh, 3.3V Synchronous DRAMs with SPD GENERAL DESCRIPTION FEATURE The Samsung KMM374S823CTS is a 8M bit x 72 Synchronous Dynamic RAM high density memory module. The Samsung |
OCR Scan |
M374S823CTS KMM374S823CTS PC100 8Mx72 400mil 168-pin M374S823CT | |
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KMM366S823CTS-GLContextual Info: KMM366S823CTS PC100 Unbuffered DIMM Revision History Revision 0.1 Mar. 24, 1999 - Changed "Detail C" in PCB Dimension. - Changed decoupling capacitance from two 0.1uF to one 0.1uF and one 0.33 uF. Rev.0.1 Mar 1999 KMM366S823CTS PC100 Unbuffered DIMM KMM366S823CTS SDRAM DIMM |
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KMM366S823CTS PC100 KMM366S823CTS 8Mx64 400mil 168-pin KMM366S823CTS-GL | |
Contextual Info: KMM466S823CT2 Preliminary 144pin SDRAM SODIMM Revision History Revision 2 August 1998 1. C orrect DQ No. in Fuctionai Block Diagram. Change DQ8 ~ DQ15 to DQO ~ DQ7. REV. 2 August 1998 ELECTRCMCS Preliminary 144pin SDRAM SODIMM KMM466S823CT2 KMM466S823CT2 SDRAM SODIMM |
OCR Scan |
KMM466S823CT2 144pin KMM466S823CT2 400mil 144-pin | |
Contextual Info: Preliminary KMM466S823CT3_144pin SDRAM SODIMM Revision History Revision 2 August 1998 1. C orrect DQ No. in Fuctionai Block Diagram. Change DQ8 ~ DQ15 to DQO ~ DQ7. REV. 2 August 1998 ELECTRCMCS Preliminary KMM466S823CT3_144pin SDRAM SODIMM |
OCR Scan |
KMM466S823CT3_ 144pin KMM466S823CT3 400mil 144-pin KMM466S823CT3 | |
km48s2020ct
Abstract: S823B 4MX16 54-PIN u108h KM48S2020 44s16030
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OCR Scan |
KM44S4020CT KM48S2020CT KM416S1020CT KM416S1021CT KM44S16020BT KM48S8020BT KM416S4020BT KM416S4021BT KM44S160308T KM48S8030BT S823B 4MX16 54-PIN u108h KM48S2020 44s16030 | |
KMM374S823CTF-G0Contextual Info: PC66 SDRAM MODULE KMM374S823CTF KMM374S823CTF SDRAM DIMM 8Mx72 SDRAM DIMM with ECC based on 8Mx8, 4Banks, 4K Refresh, 3.3V Synchronous DRAMs with SPD GENERAL DESCRIPTION FEATURE The Samsung KMM374S823CTF is a 8M bit x 72 Synchronous Dynamic RAM high density memory module. The Samsung |
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KMM374S823CTF KMM374S823CTF 8Mx72 400mil 168-pin KM48S8030CT KMM374S823CTF-G0 | |
KMM466S823CT3-F0Contextual Info: KMM466S823CT3 Preliminary 144pin SDRAM SODIMM Revision History Revision 2 August 1998 1. Correct DQ No. in Fuctional Block Diagram. Change DQ8 ~ DQ15 to DQ0 ~ DQ7. REV. 2 August 1998 Preliminary 144pin SDRAM SODIMM KMM466S823CT3 KMM466S823CT3 SDRAM SODIMM |
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KMM466S823CT3 144pin KMM466S823CT3 8Mx64 400mil 144-pin KMM466S823CT3-F0 | |
KMM366S823CTF-G0
Abstract: KMM366S823CTF
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KMM366S823CTF KMM366S823CTF 8Mx64 400mil 168-pin KM48S8030CT KMM366S823CTF-G0 | |
KMM366S823CTS
Abstract: KMM366S823CTS-GH KMM366S823CTS-G8 KMM366S823CTS-GL
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KMM366S823CTS PC100 KMM366S823CTS 8Mx64 400mil 168-pin KMM366S823CTS-GH KMM366S823CTS-G8 KMM366S823CTS-GL | |
nk401
Abstract: AM29V800 S3C3410 S3C3410X JEENI ARM7 pin discription and programming ka78r33 set date pSOS pROBE SMDK40100 SVC32
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40-S3-C3410X-062001 S3C3410X 16-Bit S3C3410X SMDK40100 SMDK40100 16/32-bit nk401 AM29V800 S3C3410 JEENI ARM7 pin discription and programming ka78r33 set date pSOS pROBE SVC32 | |
Contextual Info: PC100 SDRAM MODULE KM M374S823CTS KMM374S823CTS SDRAM DIMM 8Mx72 SDRAM DIMM with ECC based on 8Mx8, 4Banks, 4K Refresh, 3.3V Synchronous DRAMs with SPD GENERAL DESCRIPTION FEATURE The Samsung KMM374S823CTS is a 8M bit x 72 Synchronous • Performance range |
OCR Scan |
PC100 M374S823CTS KMM374S823CTS 8Mx72 M374S823CTS KMM374S823CTS-G8 125MHz 400mil KMM374S823CTS-GI- |