7C512 Search Results

AS7C31024-12TC

Abstract: AS7C1024-15TJC
Contextual Info:  $6& $6& .ð&02665$0 &RPPRQ,2 IDPLO\ HDWXUHV • TTL/LVTTL-compatible, three-state I/O • 32-pin JEDEC standard packages - 300 mil PDIP and SOJ Socket compatible with 7C512 64Kx8) - 400 mil SOJ - 8mm × 20mm TSOP • ESD protection ≥ 2000 volts

AS7C1024-15TJC

Abstract: AS7C1024L-20JC AS7C31024-12TC AS7C1024-10JC
Contextual Info:  $6& $6&/ $6& $6&/ .ð&02665$0 &RPPRQ,2 IDPLO\ HDWXUHV • TTL/LVTTL-compatible, three-state I/O • 32-pin JEDEC standard packages - 300 mil PDIP and SOJ Socket compatible with 7C512 64Kx8) - 400 mil SOJ - 8mm × 20mm TSOP

Contextual Info:  $6& $6&/ $6& $6&/ .ð&02665$0 &RPPRQ,2 IDPLO\ HDWXUHV • TTL/LVTTL-compatible, three-state I/O • 32-pin JEDEC standard packages - 300 mil PDIP and SOJ Socket compatible with 7C512 64Kx8) - 400 mil SOJ - 8mm × 20mm TSOP

7C1024

Contextual Info:  $6& 9.ð&02665$0 &RPPRQ,2 HDWXUHV • TTL-compatible, three-state I/O • 28-pin JEDEC standard packages - 300 mil PDIP and SOJ Socket compatible with 7C512 and 7C1024 - 8x13.4 TSOP • ESD protection ≥ 2000 volts • Latch-up current ≥ 200 mA

Contextual Info: High Performance 128Kx8 C M O S SRAM p i AS7C1024 AS7C1024L 128Kx8 CM O S S RAM Common I/O FEATURES • Organization: 131,072 words x 8 bits • Equal access and cycle times • High speed • Easy memory expansion with CE1, CE2, OE inputs - 10/12/15/20/25/35 ns address access time

Contextual Info: High Performance 32Kx8 CMOS SRAM p i AS7C256 AS7C256L 32Kx8 CMOS SRAM Common I/O FEATURES • Organization: 32,768 words x 8 bits Equal access and cycle times • High speed Easy memory expansion with CE and OE inputs - 10/12/15/20/25/35 ns address access time

7C1024

Abstract: AS7C256
Contextual Info: AS7C256 5V 32K •8 CMOS SRAAA /Common I OV Features • O rganization: 3 2 ,7 6 8 w ords X 8 bits • H igh speed - 1 0 /1 2 /1 5 / 2 0 ns address access tim e - 3 / 3 / 4 / 5 ns o utput enable access tim e • Low pow er consum ption - Active: 660 m W m ax 10 ns cycle

Contextual Info: H ig h P erfo rm a n ce 32K X8 CMOS SRAM AS7C.256 AS7C 256L A 32KX8 CMOS SRAM Common I/O • Organization: 32,768 words x 8 bits •H ig h sp eed - 1 0 /1 2 /1 5 /2 0 /2 5 /3 5 ns address access time - 3 / 3 / 4 / 5 / 6 /8 ns output enable access time • Low power consumption

Contextual Info: High Performance 128KX8 CMOS SRAM AS7C1024 AS7C31024 128KX8 CMOS SRAM Features • Organization: 131,072 words x 8 bits • High speed - 1 0 / 1 2 / 1 5 / 2 0 / 2 5 ns address access time - 3 / 3 / 4 / 5 / 6 ns output enable access time • Low power consumption

AS7C512-20JC

Abstract: AS7C512-15pc AS7C512 10n12 AS7C512-12JC 7C256 AS7C512L AS7CS12 Static Random Access Memory SRAM 7CS12-20
Contextual Info: High-Performance p i 7C512 : 7C512L CMOS SRAM 64Kx8 CMOS SRAM Common I/O FEATURES Organization; 65,536 words x 8 bits Equal access and cycle times High speed Easy memory expansion with CE1, CE2, OE inputs - 12/15/20/25/35 ns address access time TTL-compatible, three-state I/O

Collins Electronics

Abstract: lm 3751 AS7010 NT 407 F 0637 Z05 AS7C1024-20PC LR 3441 AS7C1024 AS7C31024 AS701024-12TJC
Contextual Info: H ig h P e r f o r m a n c e 128KX8 C M O S SR A M A AS7C1024 AS7C31024 128KX8 CMOS SRAM Features • Organization: 131,072 words x 8 bits • High speed - 1 0 / 1 2 / 1 5 / 2 0 / 2 5 ns address access time - 3 / 3 / 4 / 5 / 6 n s output enable access time

Contextual Info: H i ” h Pi i f o r n i . i i H i BB \S7C2S6 A Ì Z K '- “ iZ K x8 M O S SRAM ü \S7C2S6I 2 K X K (’M O S S R A M (Corninoli J / 0 ) • Easy m em ory expansion w ith CE and OE inputs • TTL-compatible, three-state I/O • 28-pin JEDEC standard packages

Contextual Info: High Performance 64KX8 CMOS SRAM 7C512 7C512L 64KX8 CMOS SRAM Features • Organization: 6 5 ,5 3 6 w ords x 8 bits • H igh speed - 1 2 / 1 5 / 2 0 / 2 5 / 3 5 ns address access time - 3 / 4 / S / 6 / 8 ns output enable access tim e • Low pow er consum ption

AS7C256

Abstract: 256x128x8 TI 344C
Contextual Info: High Performance 32Kx8 CMOS SRAM II ^ L lh . AS7C256 AS7C256L 32Kx8 CMOS SRAM Common I/O FEATURES • Organization: 32,768 words x 8 bits • Equal access and cycle times • High speed • Easy memory expansion with CE and OE inputs - 10/12/15/20/25/35 ns address access time

AS7C512-15pc

Abstract: AS7C512-20PC AC Ammeter CEI
Contextual Info: Features • TTL-com patible, three-state I/ O • O rganization: 6 5 ,5 3 6 w ords x 8 bits - 3 2 -p in JEDEC standard packages • H igh speed - 3 0 0 m il PDIP and SOJ - 1 5 / 2 0 / 2 5 ns address access time Socket com patible w ith 7 C 2 5 6 and 7 C 1 0 2 4

7C1024

Contextual Info: 6 4 K x 8 Fast S R A M ^ A S 7C 5I2 F eatures Logic B lock D iagram ♦ High Performance CMOS: tAA=12-35 ns ♦ Fast OE access: tOF=3-8 ns ♦ Low power - 688 mW 100 MHz - 27.5 mW @ 10 MHz standby - 4.25 mW @ 10 MHz standby: L version ♦ Socket compatible with 7C256,7C1024

FZJ 131

Abstract: PG-1500 PC-9800 PG1500 d75p108b UPD27C2001
Contextual Info: USER'S MANUAL NEC P G -15 0 0 CONTROLLER P C -9 8 0 0 SERIES MS-DOS -BASED c NEC Corporation 1990 Document No. E E U —1291C (0. D. No. E E U —7 0 4C ) D a te P ub lish e d July 1 9 9 5 P Printed in Japan SUMMARY OF CONTENTS CHAPTER 1 GENERAL.

AS7C256-20JC

Abstract: AS7C256 taa 723 7C256-10 7C256-12 7C256-15 AS7C256L AS7C256-15PC 7C1024
Contextual Info: High Performance 32Kx8 CMOS SRAM AS7C256 AS7C256L 32K×8 CMOS SRAM Common I/O FEATURES • Organization: 32,768 words × 8 bits • Equal access and cycle times • High speed • Easy memory expansion with CE and OE inputs – 10/12/15/20/25/35 ns address access time

AS7C512-20JC

Abstract: AS7C512-15pc AS7C512 AS7C512-15JC 7C1024 64KX8 7C256
Contextual Info: H ig h P e r fo r m a n c e 64K X 8 A S 7 C 5 12 II A C M O S SRAM 6 4 K X 8 C M O S SR A M • O rganization: 6 5 ,5 3 6 w o rd s x 8 bits • H igh speed • • • • • TTL-com patible, three-state I /O - 3 2 -p in JEDEC standard packages - 3 0 0 m il PDIP and SOJ

AS7C512-20JC

Abstract: AS7C512 AS7C512-15pc transistor sb 772 AS7C512-12JC AS7C512L-20JC ES 95 SB Plastic 32-pin 300 mil SOIC 7C256 AS7C512-12PC
Contextual Info: High Performance 64Kx8 CMOS SRAM 7C512 7C512L 64K×8 CMOS SRAM Features • Organization: 65,536 words × 8 bits • High speed - 12/15/20/25/35 ns address access time - 3/4/5/6/8 ns output enable access time • Low power consumption - Active: 688 mW max 12 ns cycle

Contextual Info: High-Performance 64Kx8 CMOS SRAM p i 7C512 7C512L 64Kx8 CMOS SRAM Common I/O FEATURES Equal access and cycle times • Organization; 65,536 words x 8 bits • Highspeed • Easy memory expansion with CE1, CE2, OE inputs - 12/15/20/25/35 ns address access time

Contextual Info: High Performance A S7C 512 64K X 8 C M O S SRA M 64Kx8 CMOS SRAM Features • T T L -co m p atib le, th re e -sta te I / O - 3 2 -p in JEDEC sta n d a rd packages - 3 0 0 m il PDIP a n d SOJ - 1 5 / 2 0 / 2 5 n s ad d re ss access tim e SRAM • O rg a n iz a tio n : 6 5 ,5 3 6 w o r d s x 8 b its

Contextual Info: H igh Perform ance A S7C 512 64KX8 A S7C 512L C M O S SRA M 64K X 8 CMOS SRAM • Organization: 65,536 words x 8 bits • High speed - 1 2 /1 5 /2 0 /2 5 /3 5 ns address access time - 3 / 4 / 5 / 6 / 8 ns output enable access time • Low pow er consumption

Contextual Info: Features • Organization: 32,768 words x 8 bits • High speed - 1 0 /1 2 /1 S /2 0 ns address access time - 3 / 3 / 4 / 5 ns output enable access time • Low power consumption - Active: 660 mW max 10 ns cycle - Standby: 11 mW max, CMOS I/O - Very low DC component in active power