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    VITERBI ALGORITHM Search Results

    VITERBI ALGORITHM Result Highlights (5)

    Part ECAD Model Manufacturer Description Download Buy
    BQ2031SN-A5TR Texas Instruments Switch-mode Lead-Acid Battery Charger with User-Selectable Charge Algorithms 16-SOIC 0 to 0 Visit Texas Instruments Buy
    BQ2031SN-A5TRG4 Texas Instruments Switch-mode Lead-Acid Battery Charger with User-Selectable Charge Algorithms 16-SOIC 0 to 0 Visit Texas Instruments Buy
    BQ2031SN-A5 Texas Instruments Switch-mode Lead-Acid Battery Charger with User-Selectable Charge Algorithms 16-SOIC 0 to 0 Visit Texas Instruments Buy
    BQ2031PN-A5E4 Texas Instruments Switch-mode Lead-Acid Battery Charger with User-Selectable Charge Algorithms 16-PDIP 0 to 0 Visit Texas Instruments Buy
    BQ2031PN-A5 Texas Instruments Switch-mode Lead-Acid Battery Charger with User-Selectable Charge Algorithms 16-PDIP 0 to 0 Visit Texas Instruments Buy

    VITERBI ALGORITHM Datasheets Context Search

    Catalog Datasheet MFG & Type PDF Document Tags

    Viterbi Trellis Decoder

    Abstract: Viterbi Decoder branch metric viterbi algorithm Convolutional LFX1200B polynomials parallel viterbi convolution viterbi viterbi convolution
    Text: Viterbi Decoder March 2003 IP Data Sheet Features General Description • Parameterizable Viterbi decoder Viterbi decoding is an efficient algorithm for decoding convolutionally encoded sequences. In the Viterbi Decoder, the convolutional code sequences that have been corrupted by channel noise are decoded back to their original


    Original     		PDF LFX1200B, FE680, Viterbi Trellis Decoder Viterbi Decoder branch metric viterbi algorithm Convolutional LFX1200B polynomials parallel viterbi convolution viterbi viterbi convolution

    GSM Viterbi

    Abstract: Viterbi Decoder Trellis branch metric Convolutional trellis 5/6 decoder viterbi Viterbi Trellis Decoder SC140 SP10
    Text: How to Implement a Viterbi Decoder on the StarCore SC140 Application Note Abstract The application note describes how to implement an efficient Viterbi decoder on the StarCore SC140. It begins with an overview of convolutional encoding and Viterbi decoding. The overview is followed by a description of the StarCore


    Original     		PDF SC140 SC140. SC140 GSM Viterbi Viterbi Decoder Trellis branch metric Convolutional trellis 5/6 decoder viterbi Viterbi Trellis Decoder SP10

    matched filter matlab codes

    Abstract: matched filter hdl codes branch metric Viterbi Decoder viterbi matlab
    Text: Viterbi Compiler MegaCore Function June 2001 User Guide 101 Innovation Drive San Jose, CA 95134 408 544-7000 http://www.altera.com A-UG-VITERBI-2.1 Viterbi Compiler MegaCore Function User Guide Altera, ACEX, APEX, APEX 20K, FLEX, FLEX 10KE, MAX+PLUS II, MegaCore, MegaWizard, OpenCore, Quartus, and Quartus II


    Original     		PDF

    XCV5LX50

    Abstract: branch metric parallel viterbi convolution Convolutional Encoding Viterbi Decoding Using DSP
    Text: Viterbi Decoder v6.1 DS247 May 17, 2006 Product Specification Introduction The Viterbi Decoder is used in many Forward Error Correction FEC applications and in systems where data are transmitted and subject to errors before reception. The Viterbi Decoder is compatible with many


    Original     		PDF DS247 IESS-308/309. XCV5LX50 branch metric parallel viterbi convolution Convolutional Encoding Viterbi Decoding Using DSP

    B1137

    Abstract: 2n2 f250 branch metric viterbi algorithm Convolutional Encoder TMS320C6416 Transistor y2n TMS320C6000 TR45
    Text: Application Report SPRA750D - September 2003 Using TMS320C6416 Coprocessors: Viterbi Coprocessor VCP Jelena Nikolic-Popovic Digital Signal Processing Solutions ABSTRACT Viterbi Coprocessor (VCP) is a programmable peripheral for decoding of convolutional


    Original     		PDF SPRA750D TMS320C6416 B1137 2n2 f250 branch metric viterbi algorithm Convolutional Encoder Transistor y2n TMS320C6000 TR45

    Trellis

    Abstract: viterbi IESS-308/309 Viterbi Trellis Decoder viterbi decoder for tcm decoders viterbi convolution express card DVB IESS-308/309 XAPP551 XC3S100E
    Text: Viterbi Decoder v6.2 DS247 October 10, 2007 Product Specification Introduction The Viterbi Decoder is used in many Forward Error Correction FEC applications and in systems where data are transmitted and subject to errors before reception. The Viterbi Decoder is compatible with many


    Original     		PDF DS247 IESS-308/309. Trellis viterbi IESS-308/309 Viterbi Trellis Decoder viterbi decoder for tcm decoders viterbi convolution express card DVB IESS-308/309 XAPP551 XC3S100E

    Viterbi Trellis Decoder

    Abstract: IESS-308/309 phase noise 5VLX30 IESS-308/309 viterbi IESS-308/309 FPGA Virtex-6 LXT 6VLX75T viterbi convolution spartan-6fpgas Viterbi Decoder
    Text: Viterbi Decoder v7.0 DS247 June 24, 2009 Product Specification Introduction The Viterbi Decoder is used in many Forward Error Correction FEC applications and in systems where data are transmitted and subject to errors before reception. The Viterbi Decoder is compatible with many


    Original     		PDF DS247 IESS-308/309. Viterbi Trellis Decoder IESS-308/309 phase noise 5VLX30 IESS-308/309 viterbi IESS-308/309 FPGA Virtex-6 LXT 6VLX75T viterbi convolution spartan-6fpgas Viterbi Decoder

    Puncturing vhdl

    Abstract: verilog code for BPSK matched filter hdl codes binary multiplier gf Vhdl code Convolutional Puncturing Pattern convolutional viterbi viterbi algorithm tcl script ModelSim
    Text: Viterbi Compiler MegaCore Function November 2001 User Guide 101 Innovation Drive San Jose, CA 95134 408 544-7000 http://www.altera.com A-UG-VITERBI-3.0 Viterbi Compiler MegaCore Function User Guide Copyright  2001 Altera Corporation. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all


    Original     		PDF 00e-01 00e-02 00e-03 00e-04 00e-05 00e-06 00e-07 Puncturing vhdl verilog code for BPSK matched filter hdl codes binary multiplier gf Vhdl code Convolutional Puncturing Pattern convolutional viterbi viterbi algorithm tcl script ModelSim

    Untitled

    Abstract: No abstract text available
    Text: ispLever CORE TM Viterbi Decoder User’s Guide October 2005 ipug04_02.0 Lattice Semiconductor Viterbi Decoder User’s Guide Introduction Lattice’s Viterbi Decoder core is a parameterizable core for decoding different combinations of convolutionally encoded sequences. The decoder core supports various code rates, constraint lengths and generator polynomials.


    Original     		PDF ipug04 LFX1200B, FE680,

    circuit diagram of speech recognition

    Abstract: block diagram of speech recognition intel AP-569 AP-811 24364 AP-81
    Text: AP-811 Hidden Markov Model with Viterbi Decoding Using Streaming SIMD Extensions to Evaluate a Hidden Markov Model with Viterbi Decoding Version 2.1 01/99 Order Number: 243645-002 02/04/99 AP-811 Hidden Markov Model with Viterbi Decoding Information in this document is provided in connection with Intel products. No license, express or


    Original     		PDF AP-811 circuit diagram of speech recognition block diagram of speech recognition intel AP-569 24364 AP-81

    SPRA071

    Abstract: GSM Viterbi Qualcomm application note Convolutional qualcomm convolutional decoder TMS320C53-Based Viterbi Trellis Decoder texas Q1401 TMS320C54X AN-1401
    Text: Viterbi Decoding Techniques in the TMS320C54x Family Application Report 1996 Digital Signal Processing Products Printed in U.S.A. 0696 SPRA071 Viterbi Decoding Techniques in the TMS320C54x Family Henry Hendrix Member, Group Technical Staff SPRA071 June 1996


    Original     		PDF TMS320C54x SPRA071 SPRA071 GSM Viterbi Qualcomm application note Convolutional qualcomm convolutional decoder TMS320C53-Based Viterbi Trellis Decoder texas Q1401 AN-1401

    low frequency bpsk modulator ic

    Abstract: G110 g21 Transistor STEL-2060C BPSK DEMODULATORS G21P2
    Text: STEL-2060C/CR Data Sheet STEL-2060C/CR 45 Mbps Viterbi Decoder R FUNCTIONAL DESCRIPTION FEATURES • 45 Mbps Operating Rate ■ Constraint Length K = 7 G1 = 1718 Convolutional encoding and Viterbi decoding are used to provide forward error correction FEC which improves


    Original     		PDF STEL-2060C/CR STEL-2060C low frequency bpsk modulator ic G110 g21 Transistor BPSK DEMODULATORS G21P2

    branch metric

    Abstract: Viterbi Decoder viterbi algorithm branch metric report trellis 5/6 decoder Viterbi Trellis Decoder texas DSP56300 DSP56600 IS-136 Convolutional decoder
    Text: Implementing Viterbi Decoders Using the VSL Instruction on DSP Families DSP56300 and DSP56600 by Dana Taipale This application report describes how to generate, from a set of convolutional code polynomials, the assembly code needed for implementation of a Viterbi decoder.


    Original     		PDF DSP56300 DSP56600 APR40/D branch metric Viterbi Decoder viterbi algorithm branch metric report trellis 5/6 decoder Viterbi Trellis Decoder texas DSP56600 IS-136 Convolutional decoder

    B1137

    Abstract: branch metric trellis 5/6 decoder TMS320C6000 TMS320C6416 TR45 SPRU533 convolutional
    Text: Application Report SPRA750 - June 2001 Using TMS320C6416 Coprocessors: Viterbi Coprocessor VCP Jelena Nikolic-Popovic Digital Signal Processing Solutions ABSTRACT Viterbi Coprocessor (VCP) is a programmable peripheral for decoding of convolutional codes, integrated into Texas Instruments’ TMS320C6416 DSP device. The VCP is controlled


    Original     		PDF SPRA750 TMS320C6416 B1137 branch metric trellis 5/6 decoder TMS320C6000 TR45 SPRU533 convolutional

    EPF10K30ETC144-1

    Abstract: EPF10K50ETC144-1 EPF20K EP20K100E EP20K60E EPF10K100EQC208-1
    Text: White Paper Area Optimized Soft Decision Viterbi Decoder Functions Introduction The Altera® area optimized, soft decision Viterbi decoder HammerCores are optimized for APEX 20K, FLEX®10K and FLEX 6000 devices. You can parameterize the devices by implementing any number of standard decoders or you


    Original     		PDF APEXTM20K, EPF10K30ETC144-1 EPF10K50ETC144-1 EPF20K EP20K100E EP20K60E EPF10K100EQC208-1

    branch metric

    Abstract: Convolutional Encoder details and application GSM Viterbi SC140 SP10 SP11 SP12 SP14
    Text: Freescale Semiconductor, Inc. How to Implement a Viterbi Decoder on the StarCore SC140 Freescale Semiconductor, nc. I Application Note Abstract The application note describes how to implement an efficient Viterbi decoder on the StarCore SC140. It begins with an overview of convolutional encoding and


    Original     		PDF SC140 SC140. SC140 branch metric Convolutional Encoder details and application GSM Viterbi SP10 SP11 SP12 SP14

    Untitled

    Abstract: No abstract text available
    Text: Block Viterbi Decoder User’s Guide June 2010 IPUG32_02.7 Table of Contents Chapter 1. Introduction . 4 Quick Facts . 4


    Original     		PDF IPUG32 2004-OFDM LFXP2-17E-7F484C D-2009 12L-1

    Q1900

    Abstract: No abstract text available
    Text: Q1900 VITERBI/TRELLIS DECODER FEATURES • Viterbi Mode Rates V3 , V2 , 3/ a and 7M • Data Rates up to 30 Mbps for Viterbi Mode and • Trellis Mode Rates 2/3 and 3/4 • Full Duplex Encode and Decode in Both Viterbi and Trellis Modes • Large Coding Gains at Eb/No of 10 5


    OCR Scan     		PDF Q1900 16-PSK) 84-pin Q1900

    Untitled

    Abstract: No abstract text available
    Text: Q1650 k -7 MULTI-CODE RATE VITERBI DECODER 2.5,20, 25 Mbps Data Rates Technical Data Sheet Q1650 Viterbi Decoder 2 Other QUALCOMM VLSI Products • Viterbi Decoders - 256 Kbps to 25 Mbps Maximum Data Rates • Direct Digital Synthesizers DDS •1.6 GHz Phase Locked Loop Frequency Synthesizers


    OCR Scan     		PDF Q1650 Q1650 DL90-1650

    Q1650C1N

    Abstract: Qualcomm LTE system diagram scrambler v.35 algorithm Q1650C-3N Qualcomm application note Viterbi oqpsk vsat qualcomm IQ diagram qualcomm qualcomm IQ demodulator block diagram of qualcomm lte
    Text: Q u a lco m m Q1650 k=7 MULTI-CODE RATE VITERBI DECODER 2.5, 10, 25 Mbps Data Rates Technical Data Sheet Q l 650 Viterbi Decoder 2 Other QUALCOMM VLSI Products • Viterbi Decoders - 256 Kbps to 25 Mbps Maximum Data Rates • Pragmatic Trellis Modulation Codecs


    OCR Scan     		PDF Q1650 DL90-1650 Q1650C1N Qualcomm LTE system diagram scrambler v.35 algorithm Q1650C-3N Qualcomm application note Viterbi oqpsk vsat qualcomm IQ diagram qualcomm qualcomm IQ demodulator block diagram of qualcomm lte

    Viterbi Trellis Decoder

    Abstract: DSP6001 Scans-00135050 32QAM 32QAM modulation Viterbi Decoder XO 18 DSP56001 "vlsi technology" Convolutional Encoder
    Text: APR6/D Rev. 1 ^ Convolutional Encoding and Viterbi Decoding Using the DSP56001 with a V.32 Modem Trellis Example Motorola Digitai Signal Processors Convolutional Encoding and Viterbi Decoding Using the DSP56001 with a V.32 Modem Trellis Example by Dion Messer Funderburk


    OCR Scan     		PDF DSP56001 COM-19, 1ATX25284â Viterbi Trellis Decoder DSP6001 Scans-00135050 32QAM 32QAM modulation Viterbi Decoder XO 18 "vlsi technology" Convolutional Encoder

    qualcomm application note

    Abstract: Q1650C-3N InMarSat demodulator Q1650 qualcomm convolutional decoder scrambler satellite q0165 AN1650-1 encoder puncture qualcomm viterbi convolution
    Text: 01650 k=7 MULTI-CODE RATE VITERBI DECODER 2 .5 ,1 0 ,2 5 M b p s D A T A R A T ES Products ^00333ti □□□DflSD T7S \ C O NTENTS Other QUALCOMM VLSI Products • Viterbi Decoders — 256 Kbps to


    OCR Scan     		PDF 00333ti 10-bit 12-bit T00333b qualcomm application note Q1650C-3N InMarSat demodulator Q1650 qualcomm convolutional decoder scrambler satellite q0165 AN1650-1 encoder puncture qualcomm viterbi convolution

    scrambler satellite

    Abstract: AN1650-2 Viterbi Decoder qualcomm IQ AN1650-1 R0702 InMarSat modulator Q1650 qualcomm 1110 84-PIN
    Text: I Q ualco / w va Q1650 k = 7 M U L T I-C O D E RATE V ITERBI D EC O D ER 2.5, 10, 25 Mbps Data Rates Technical D a ta Sheet Powered by ICminer.com Electronic-Library Service CopyRight 2003 Q1650 Viterbi Decoder 2 Other QUALCOMM VLSI Products • Viterbi Decoders - 256 Kbps to 25 Mbps Maximum Data Rates


    OCR Scan     		PDF Q1650 Q1650 scrambler satellite AN1650-2 Viterbi Decoder qualcomm IQ AN1650-1 R0702 InMarSat modulator qualcomm 1110 84-PIN

    Qualcomm application note

    Abstract: AN1650-2 AN1650-1 Setting Soft-Decision Thresholds for Viterbi Qualcomm Application Note AN1650-2 IESS-308 sCRAMBLER IESS-308 InMarSat demodulator qualcomm Application Note AN1650 encoder puncture qualcomm
    Text: I Q ualco / w va Q1650 k = 7 M U L T I-C O D E RATE V ITERBI D EC O D ER 2.5, 10, 25 Mbps Data Rates Technical D a ta Sheet This Material Copyrighted By Its Respective Manufacturer Q1650 Viterbi Decoder 2 Other QUALCOMM VLSI Products • Viterbi Decoders - 256 Kbps to 25 Mbps Maximum Data Rates


    OCR Scan     		PDF Q1650 Q1650 Qualcomm application note AN1650-2 AN1650-1 Setting Soft-Decision Thresholds for Viterbi Qualcomm Application Note AN1650-2 IESS-308 sCRAMBLER IESS-308 InMarSat demodulator qualcomm Application Note AN1650 encoder puncture qualcomm