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    AMD EF-DI-VITERBI-SITE

    SITE LICENSE VITERBI DECODER
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    AMD EFR-DI-VITERBI-SITE

    VITERBI DECODER IP CORE
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    AMD EFR-DI-VITERBI-WW

    LOGICORE, VITERBI DECODER (CONVOLUTIONAL ENCODER FREE), WORLDWIDE LICENSE RENEWAL - Virtual or Non-Physical Inventory (Software & Literature) (Alt: EFR-DI-VITERBI-WW)
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    Altera Corporation IPR-VITERBI/SS

    Development Software Viterbi Low-Speed MegaCore RENEWAL
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    Altera Corporation IPR-VITERBI/HS

    Development Software Viterbi High-Speed MegaCore RENEWAL
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    VITERBI Datasheets (2)

    Part ECAD Model Manufacturer Description Curated Datasheet Type PDF
    Viterbi Decoder Lattice Semiconductor Viterbi Decoder Data Sheet Original PDF
    Viterbi Decoders Altera Viterbi Decoders White Paper Original PDF

    VITERBI Datasheets Context Search

    Catalog Datasheet MFG & Type PDF Document Tags

    TMDX28069USB

    Abstract: controlstick TMS320x piccolo TMS320c2000 mcu controlstick TMX320F28069 F2806x TMDXDOCK28069 F28069 TMX320F28069PNA CNC DRIVES
    Text: Piccolo MCUs: TMS320F2806x 15+ new C2000™ Piccolo MCUs offering floating-point precision and increased math capabilities What tools are there? 3 key new attributes for F2806x • Floating-point ease of use and performance in a Piccolo package • New features like USB, VCU Viterbi


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    PDF TMS320F2806x C2000TM F2806x 256KB 100KB F28069 TMDX28069USB controlstick TMS320x piccolo TMS320c2000 mcu controlstick TMX320F28069 F2806x TMDXDOCK28069 TMX320F28069PNA CNC DRIVES

    disc drive servo demodulator

    Abstract: transistor servo drive 32P4918B
    Text: SSI 32P4918B PR4ML Read Channel with 8/9 ENDEC and Area Detect Servo March 1998 Functional blocks include a bi-directional serial port, an automatic gain control amplifier, a programmable filter, an offset canceller, a peak detecting pulse qualifier, an adaptive transversal filter, a Viterbi qualifier


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    PDF 32P4918B disc drive servo demodulator transistor servo drive 32P4918B

    vhdl code for qam

    Abstract: vhdl code for 555
    Text: Preliminary Product Brief August 2000 VUDU 2.0—Viterbi Universal Decoding Unit Overview VUDU is a VHDL software tool that allows the flexible and rapid prototyping of a wide variety of Viterbi decoders. With the aid of a synthesis tool and Lucent's ORCA FPGAs, it is possible to configure


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    PDF PB00-084FPGA vhdl code for qam vhdl code for 555

    NCO10

    Abstract: CXD1961AQ TUD32 TUD14 TUD22 AT/TDB1-0524SU
    Text: CXD1961AQ DVB-S Frontend IC QPSK demodulation + FEC Preliminary Description The CXD1961AQ is a single chip DVB compliant Satellite Broadcasting Frontend IC, including dual A/D converter for analog baseband I/Q input, QPSK demodulator, Viterbi decoder Reed-Solomon decoder


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    PDF CXD1961AQ CXD1961AQ 100PIN QFP-100P-L01 QFP100-P-1420 42/COPPER NCO10 TUD32 TUD14 TUD22 AT/TDB1-0524SU

    LD4300

    Abstract: gpr detector viterbi
    Text: LD4300 GALAXY Advance Information FEATURES General • 150 - 850 Mbits/sec data rate operation · Extended Class 4 Partial Response with Viterbi detection EPRML system or · Generalized Class 4 Partial Response with Viterbi detection (GPRML) system · Rate 32/34 and 96/102 Trellis Constraint code with Post-Processor


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    PDF LD4300 LD4300 gpr detector viterbi

    cs3411

    Abstract: viterbi decoder soft bit viterbi
    Text: CS3411QL Viterbi Decoder k=7, r=1/2 Data Sheet Executive Summary Module BSC256FFT Device QuickDSP QL7180 -7 Worst Case Speed Grade 3714/3966 (91.2%/98.4%) Area (no buffers/ buffered) 18 of 36 (50%) RAM Cells used 36 MHz Maximal Clock Frequency Device Highlights


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    PDF CS3411QL BSC256FFT QL7180 CS3411 viterbi decoder soft bit viterbi

    vhdl code for branch metric unit

    Abstract: processor control unit vhdl code processor control unit vhdl code download vhdl coding for hamming code branch metric vhdl code 16 bit processor hamming decoder vhdl code 5 to 32 decoder using 3 to 8 decoder vhdl code Radix selection unit radix 2 verilog
    Text: VITERBI_DEC Viterbi Decoder January 10, 2000 Product Specification AllianceCORE Facts CSELT S.p.A Via G. Reiss Romoli, 274 I-10148 Torino, Italy Phone: +39 011 228 7165 Fax: +39 011 228 7003 E-mail: viplibrary@cselt.it URL: www.cselt.it Features • Supports Spartan, Spartan™-II, Virtex™, and


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    PDF I-10148 vhdl code for branch metric unit processor control unit vhdl code processor control unit vhdl code download vhdl coding for hamming code branch metric vhdl code 16 bit processor hamming decoder vhdl code 5 to 32 decoder using 3 to 8 decoder vhdl code Radix selection unit radix 2 verilog

    5 to 32 decoder using 3 to 8 decoder vhdl code

    Abstract: branch metric BPSK modulation VHDL CODE verilog code for BPSK 5 to 32 decoder using 3 to 8 decoder verilog qpsk modulation VHDL CODE QPSK using xilinx vhdl code for modulation X9009 Viterbi Decoder
    Text: Soft-Decision Viterbi Decoder January 10, 2000 Product Specification AllianceCORE Facts CAST, Inc. 24 White Birch Drive Pomona, New York 10907 USA Phone: +1 914-354-4945 Fax: +1 914-354-0325 E-Mail: info@cast-inc.com URL: www.cast-inc.com Features • •


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    scrambler v.35 algorithm

    Abstract: scrambler satellite v.35 scrambler v.35 diagram CNT-240 STEL-2070A bpsk modulator low frequency bpsk modulator ic CNT2423-0 CNT160 convolutional
    Text: STEL-2070A Data Sheet STEL-2070A Dual Constraint Length K=7,9 Convolutional Encoder Viterbi Decoder R FEATURES • Dual Constraint Length: 7 or 9 ■ Coding Gain: 5.2 dB (@ 10-5 BER, K = 7) ■ Rate 1/2 6.0 dB (@ 10-5 BER, K = 9) ■ Three Bit Soft Decision Inputs in Signed


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    PDF STEL-2070A scrambler v.35 algorithm scrambler satellite v.35 scrambler v.35 diagram CNT-240 STEL-2070A bpsk modulator low frequency bpsk modulator ic CNT2423-0 CNT160 convolutional

    STEL-2030C

    Abstract: scrambler v.35 algorithm 74AC298 IESS-308 sCRAMBLER 74AC74 84-PIN STEL2030B qpsk encoder 16 bit scrambler satellite v.35 viterbi algorithm
    Text: STEL-2030C Data Sheet STEL-2030C 17 Mbps Convolutional Encoder Viterbi Decoder R FEATURES FUNCTIONAL DESCRIPTION n 17 Mbps MAX. OPERATING DATA RATE n CONSTRAINT LENGTH K = 7 G1 = 1718, G2 = 1338 n MULTIPLE DEVICES CAN BE MULTIPLEXED TO GIVE HIGHER DATA RATES


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    PDF STEL-2030C STEL-2030C scrambler v.35 algorithm 74AC298 IESS-308 sCRAMBLER 74AC74 84-PIN STEL2030B qpsk encoder 16 bit scrambler satellite v.35 viterbi algorithm

    g3d0

    Abstract: PLCC 68 intel package dimensions "7 Bit Shift Register" data scrambler reference signal every symbols STEL-5268 2040a convolutional scrambler satellite v.35
    Text: STEL-2040A Data Sheet STEL-2040A Convolutional Encoder Viterbi Decoder R FEATURES • Constraint Length 7 ■ Coding Gain of 5.2 dB @ 10-5 BER, Rate 1/2 ■ Rates 1/3 , 1/2 , 2/3* and 3/4* (*Punctured) ■ Industry Standard Polynomials ■ Built in BER Monitor


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    PDF STEL-2040A 68-pin 70301A g3d0 PLCC 68 intel package dimensions "7 Bit Shift Register" data scrambler reference signal every symbols STEL-5268 2040a convolutional scrambler satellite v.35

    Viterbi Decoder

    Abstract: vhdl code for viterbi decoder
    Text: Viterbi Compiler Errata Sheet December 2006, Compiler Version 7.0 This document addresses known errata and documentation issues for the Viterbi Compiler version 7.0. Errata are functional defects or errors, which may cause the Viterbi Compiler to deviate from published


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    Convolutional Encoder

    Abstract: 171OCT Convolutional convolutional encoder interleaving BYP 303 ENCODER GMBH A112 AN2835 MRC6011 x8 encoder
    Text: Freescale Semiconductor Application Note AN2835 Rev. 0, 9/2004 Building a Convolutional Encoder Using RCF Technology by Wim Rouwet Convolutional encoding is a forward error correcting FEC process associated with a Viterbi decoder on the receive side. Adding redundancy to the input data before it is sent to the


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    PDF AN2835 Convolutional Encoder 171OCT Convolutional convolutional encoder interleaving BYP 303 ENCODER GMBH A112 AN2835 MRC6011 x8 encoder

    convolutional interleave

    Abstract: ANRS02 Viterbi Decoder 80C188 AHA4210 ANRS01 ANRS07 design for block interleaver deinterleaver convolutional encoder and interleaver Ramsey Electronics
    Text: Product Specification AHA4210 RSVP Viterbi with Reed-Solomon Decoder Advanced Hardware Architectures, Inc. 2365 NE Hopkins Court Pullman, WA 99163-5601 509.334.1000 Fax: 509.334.9000 e-mail: sales@aha.com http://www.aha.com TM Advanced Hardware Architectures


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    PDF AHA4210 PS4210-1099 AHA4210 Architectu995 DT/8622/DVB, DT/8610/III-B, convolutional interleave ANRS02 Viterbi Decoder 80C188 ANRS01 ANRS07 design for block interleaver deinterleaver convolutional encoder and interleaver Ramsey Electronics

    circuit diagram of speech recognition

    Abstract: block diagram of speech recognition intel AP-569 AP-811 24364 AP-81
    Text: AP-811 Hidden Markov Model with Viterbi Decoding Using Streaming SIMD Extensions to Evaluate a Hidden Markov Model with Viterbi Decoding Version 2.1 01/99 Order Number: 243645-002 02/04/99 AP-811 Hidden Markov Model with Viterbi Decoding Information in this document is provided in connection with Intel products. No license, express or


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    PDF AP-811 circuit diagram of speech recognition block diagram of speech recognition intel AP-569 24364 AP-81

    Stanford Telecom

    Abstract: No abstract text available
    Text: STEL-2048 Data Sheet STEL-2048/CM 2.048 Mbps Viterbi Decoder STANFORD TELECOM* 6505242 DQDEbfib TSE • FEATURES FUNCTIONAL DESCRIPTION H 2.048 Mbps Maximum Operating Rate Convolutional encoding and Viterbi decoding are used to provide forward error correction FEC which improves


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    PDF STEL-2048 STEL-2048/CM 84-pin STEL-2048/CM 00DE7DE STEL-2048/C Stanford Telecom

    Q1900

    Abstract: No abstract text available
    Text: Q1900 VITERBI/TRELLIS DECODER FEATURES • Viterbi Mode Rates V3 , V2 , 3/ a and 7M • Data Rates up to 30 Mbps for Viterbi Mode and • Trellis Mode Rates 2/3 and 3/4 • Full Duplex Encode and Decode in Both Viterbi and Trellis Modes • Large Coding Gains at Eb/No of 10 5


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    PDF Q1900 16-PSK) 84-pin Q1900

    OQ0256

    Abstract: Q0256 AN1650-2 T0033 iess-309 standard Viterbi oqpsk vsat InMarSat modulator Q1650 InMarSat demodulator board Satellite modem
    Text: 00256 k=7 MULTI-CODE RATE VITERBI DECODER 256 Kbps DATA RATE •iDG333b 0 0 0 0 7 b l b07 CONTENTS F O ther Q U ALC OM M VLSI Products Rate Vi Serial Mode O peration 25 Theory of O peration. 6


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    PDF iDG333b 10-bit 12-bit DL90-1654F Q0256 TD0333b OQ0256 AN1650-2 T0033 iess-309 standard Viterbi oqpsk vsat InMarSat modulator Q1650 InMarSat demodulator board Satellite modem

    A7205

    Abstract: 171OCT a7206
    Text: Philips Semiconductors Product specification Satellite Demodulator and Decoder SDD TDA8043 FEATURES • One-chip Digital Video Broadcasting (DVB) compliant demodulator and concatenated Viterbi/Reed-Solomon decoder with de-interleaver and de-randomizer BUS


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    Untitled

    Abstract: No abstract text available
    Text: ;O N Y 1_ _ _ _ _ _ _ _ _ _ _ C X D 1961 Q I DVB-S Front-end IC QPSK demodulator + FEC Preliminary Description The CXD1961Q is a single chip DVB Satellite Broadcasting Front-end IC, including dual ADC for analog I/O inputs, QPSK demodulator, Viterbi decoder, de-interleaver, Reed-Solomon decoder


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    PDF CXD1961Q CXD1961Q 100PIN LQFP-100P-L01 QFP100-P-1414-A

    Untitled

    Abstract: No abstract text available
    Text: VM65014 VTC Inc. Value the Customer ANALOG PRML CHANNEL DETECTOR 960801 PRELIMINARY FEATURES CONNECTION DIAGRAM • Register programmable user data rates from 46 to 140 Mbps • Sampled data read channel with maximum likelihood Viterbi detection • Programmable continuous-time filter with two


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    PDF VM65014

    IESS-308 sCRAMBLER

    Abstract: BIT 31936 scrambler satellite v.35 Viterbi Trellis Decoder texas IESS309 IESS-309 33-/BIT 31936
    Text: VLSI Tech n o lo gy , in c . VP17018 RPFEC FORWARD ERROR CORRECTION CIRCUIT FEATURES • Optional selection of differential encoding/decoding insertion for operation at code rates up to 7/8 • Integrates a full-featured convo­ lutional encoder and a Viterbi


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    PDF VP17018 VP17018-256 VP17018-2500 IESS-308 sCRAMBLER BIT 31936 scrambler satellite v.35 Viterbi Trellis Decoder texas IESS309 IESS-309 33-/BIT 31936

    55425

    Abstract: Maximum Likelihood block diagram
    Text: VM ÌS IS J!? ,;- 950801 FEA TU RES • Register Programmable User Data Rates From 46 to 140 Mbps • Sampled Data Read Channel With Viterbi Qualification • Programmable Continuous-Time Filter With Two Independently Variable Real Zeros and Up to 13 dB Boost


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    PDF VM65050 VM65050 55425 Maximum Likelihood block diagram

    TSS902E

    Abstract: Viterbi Decoder Viterbi Trellis Decoder Setting Soft-Decision Thresholds for Viterbi ETS-300-421
    Text: Tem ic TSS902E S e m ic o n d u c t o r s Viterbi and Reed-Solomon FEC Decoder 1. Description Digital communication channels are inherently noisy, making transmission error control essential for reliable communication at low transmit power. The TEMIC TSS902E is a single-chip Forward Error


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    PDF TSS902E TSS902E SCC9000 Viterbi Decoder Viterbi Trellis Decoder Setting Soft-Decision Thresholds for Viterbi ETS-300-421