POLYNOMIALS Search Results

74F401

Abstract: 74F401PC 74F401SC CRC-12 CRC-16 M14A MS-001 N14A CRC 9401
Contextual Info: Revised August 1999 74F401 CRC Generator/Checker General Description Features The 74F401 Cycle Redundancy Check CRC Generator/ Checker provides an advanced tool for implementing the most widely used error detection scheme in serial digital data handling systems. A 3-bit control input selects one-ofeight generator polynomials. The list of polynomials

Contextual Info: Semico n d u August 1995 t o r 74F401 CRC Generator/Checker General Description Features The ’F401 Cycle Redundancy Check CRC Generator/ Checker provides an advanced tool for implementing the most widely used error detection scheme in serial digital data handling systems. A 3-bit control input selects one-ofeight generator polynomials. The list of polynomials in­

g3d0

Abstract: PLCC 68 intel package dimensions "7 Bit Shift Register" data scrambler reference signal every symbols STEL-5268 2040a convolutional scrambler satellite v.35
Contextual Info: STEL-2040A Data Sheet STEL-2040A Convolutional Encoder Viterbi Decoder R FEATURES • Constraint Length 7 ■ Coding Gain of 5.2 dB @ 10-5 BER, Rate 1/2 ■ Rates 1/3 , 1/2 , 2/3* and 3/4* (*Punctured) ■ Industry Standard Polynomials ■ Built in BER Monitor

AT91SAM

Abstract: atmel 214
Contextual Info: Features • Provides Hardware Acceleration for determining roots of polynomials defined over a finite field • Programmable Finite Field GF 2^13 or GF(2^14) • Finds Roots of Error Locator Polynomial • Programmable Number of Roots 1. Description The PMECC Error Location Controller provides hardware acceleration for determining

Contextual Info: National Semiconductor 54F/74F401 CRC Generator/Checker General Description Features The ’F401 Cycle Redundancy Check CRC Generator/ Checker provides an advanced tool for implementing the most widely used error detection scheme in serial digital data handling systems. A 3-bit control input selects one-ofeight generator polynomials. The list of polynomials in­

Convolutional Encoder

Abstract: ispLEVER project Navigator Convolutional encoder verilog coding Convolutional Puncturing Pattern digital clock project Convolutional decoder polynomial Viterbi Decoder ispLEVER project Navigator route place
Contextual Info: Convolutional Encoder User’s Guide April 2003 ipug03_02 Lattice Semiconductor Convolutional Encoder User’s Guide Introduction Lattice’s Convolutional Encoder core is a parameterizable core for convolutional encoding of a continuous input data stream. The core allows variable code rates, constraint lengths and generator polynomials. The core also supports puncturing. Puncturing enables a large range of transmission rates and reduces the bandwidth requirement

LFSR

Abstract: c code 4 bit LFSR AN4400 code 4 bit LFSR polynomials code 24 bit LFSR simple LFSR polynomial APP4400 pseudo random numbers using lfsr
Contextual Info: Maxim > App Notes > General engineering topics Microcontrollers Keywords: microcontroller microprocessor LFSR random Jun 30, 2010 APPLICATION NOTE 4400 Pseudo random number generation using linear feedback shift registers By: Conrad Schlundt Abstract: Linear feedback shift registers are introduced along with the polynomials that completely describe them. The application note

Contextual Info: ¿/M iö SiBER 673480 Single Burst Error Recovery 1C Features/B enefits Ordering Inform ation • 15 MHz data rate PART NUMBER PACKAGE TEMPERATURE 673480 J C om • Selectable CRC or ECC polynomials • Standard 16-bit CRC-CCITT polynomial delects errors

Contextual Info: tß Semiconductor National 74F401 CRC Generator/Checker General Description Features The ’F401 Cycle Redundancy Check CRC Generator/ Checker provides an advanced tool for Implementing the most widely used error detection scheme In serial digital data handling systems. A 3-bit control input selects one-ofeight generator polynomials. The list of polynomials in­

RAID-5

Abstract: 440SP 440S PPC440 amcc 440 POWERPC-440SP
Contextual Info: PRODUCT BRIEF RAID 5/6 with PowerPC440SP/SPe High performance RAID computations with PowerPC 440S series Features • Hardware support for RAID 5 and RAID 6 calculations • PPC 440SPe+ supports polynomials 11d, 14d, and 30 others • PPC 440SP+ supports 14d

CRC 9401

Abstract: 311 pin diagram
Contextual Info: 401 54F/74F401 Connection Diagrams CRC Generator/Checker c p fT Z iN c c W | er p t r la Redundancy Check CRC Generator/Checker provides an lementing the most widely used error detection I data handling systems. A 3-bit control input 'g e n g jm j^ polynomials. The list of polynomials in­

Contextual Info: & National Semiconductor 74F401 CRC Generator/Checker General Description Features The 'F401 Cycle Redundancy Check CRC Generator/ Checker provides an advanced tool for implementing the most widely used error detection scheme in serial digital data handling systems. A 3-bit control input selects one-ofeight generator polynomials. The list of polynomials in­

scrambler satellite v.35

Abstract: IESS-308 sCRAMBLER BUS13r iess-309 standard BPSK demodulator bpsk modulation and demodulation scrambler v.35 diagram intelsat scrambler IESS309
Contextual Info: PMC r PM7018 RPFEC ERROR CORRECTION CIRCUIT DATA SHEET FEATURES • Constraint length 7 convolutional encoder polynomials 133,171 • Vrterbi decoder with up to 3 bit soft decision inputs and an 80 stage trellis • Two versions for operation at the following information data rates:

Contextual Info: ITS-90 Thermocouple Direct & Inverse Polynomials Direct Polynomials provide the thermoelectric voltage µV from a known temperature (°C); Inverse Polynomials provide the temperature (°C) from a known thermoelectric voltage (µV). Type J Thermocouples - coefficients, ci, of reference

Contextual Info: ispLever CORE TM Viterbi Decoder User’s Guide October 2005 ipug04_02.0 Lattice Semiconductor Viterbi Decoder User’s Guide Introduction Lattice’s Viterbi Decoder core is a parameterizable core for decoding different combinations of convolutionally encoded sequences. The decoder core supports various code rates, constraint lengths and generator polynomials.

scrambler satellite v.35

Abstract: scrambler v.35 algorithm branch metric g1d1 sm2c convolutional G3N1 IESS-308 sCRAMBLER
Contextual Info: STEL-2050A Data Sheet STEL-2050A Convolutional Encoder Viterbi Decoder R FEATURES • Constraint Length 7 ■ Coding Gain of 5.2 dB @ 10-5 BER, Rate 1/2 ■ Rates 1/3 , 1/2 , 2/3* and 3/4* (*Punctured) ■ Industry Standard Polynomials ■ Built in BER Monitor

STEL-5269 512

Abstract: AN 5269 qpsk transmitter STEL-5269 74HC74 decoder STEL-5268 convolutional convolutional encoder interleaving bpsk modulator STEL-5269+512
Contextual Info: STEL-5269+512 Data Sheet STEL-5269+512 Convolutional Encoder Viterbi Decoder R FEATURES • CONSTRAINT LENGTH 7 ■ CODING RATES 1/2 AND 1/3 ■ THREE BIT SOFT-DECISION INPUTS IN ■ CODING GAIN OF 6.0 dB AT 10–5 BER, RATE 1/3 ■ INDUSTRY STANDARD POLYNOMIALS

branch metric

Abstract: Viterbi Decoder viterbi algorithm branch metric report trellis 5/6 decoder Viterbi Trellis Decoder texas DSP56300 DSP56600 IS-136 Convolutional decoder
Contextual Info: Implementing Viterbi Decoders Using the VSL Instruction on DSP Families DSP56300 and DSP56600 by Dana Taipale This application report describes how to generate, from a set of convolutional code polynomials, the assembly code needed for implementation of a Viterbi decoder.

Reed-Solomon encoder algorithm

Abstract: LFX125B-04F256C LFX125B04F256C polynomials OC192 x8 encoder
Contextual Info: Reed-Solomon Encoder April 2003 IP Data Sheet Features General Description • 3- to 12-Bit Symbol Width ■ Configurable Polynomials Reed-Solomon codes are used to perform Forward Error Correction FEC . FEC introduces redundancy in the data before it is transmitted. The redundant data

branch metric

Abstract: Viterbi Decoder Viterbi Trellis Decoder Viterbi Trellis Decoder texas DSP56300 DSP56600 IS-136
Contextual Info: Freescale Semiconductor, Inc. Freescale Semiconductor, Inc. Implementing Viterbi Decoders Using the VSL Instruction on DSP Families DSP56300 and DSP56600 by Dana Taipale This application report describes how to generate, from a set of convolutional code polynomials, the assembly code needed for

Contextual Info: SiBER 673480 Single Burst Error Recovery 1C O rdering Inform ation F eatu res/ Benefits • 15 MHz data rate PART NUMBER PACKAGE TEMPERATURE 673480 J Com • Selectable CRC or ECC polynomials • Standard 16-blt CRC-CCITT polynomial detects errors • Computer-generated 32-bit ECC polynomial exceeds the

9534 diode

Abstract: transistor f401 74F401 74F401PC 74F401SC C1995 CRC-12 CRC-16 M14A N14A
Contextual Info: 74F401 CRC Generator Checker General Description Features The ’F401 Cycle Redundancy Check CRC Generator Checker provides an advanced tool for implementing the most widely used error detection scheme in serial digital data handling systems A 3-bit control input selects one-ofeight generator polynomials The list of polynomials includes CRC-16 and CRC-CCITT as well as their reciprocals

Contextual Info: TMS320TCI100 FIXEDĆPOINT DIGITAL SIGNAL PROCESSOR SPRS218H − MAY 2003 − REVISED JUNE 2006 D Highest-Performance Fixed-Point Digital D D D D D Signal Processors DSPs − 1.67-, 1.39-ns Instruction Cycle Time − 600-, 720-MHz Clock Rate − Eight 32-Bit Instructions/Cycle

atxmega128B

Abstract: 141-003 0x0D00 XMEGA Application Notes
Contextual Info: 8/16-bit Atmel XMEGA B1 Microcontroller ATxmega128B1; ATxmega64B1 Features  High-performance, low-power Atmel AVR® XMEGA® 8/16-bit Microcontroller  Nonvolatile program and data memories          64K - 128KBytes of in-system self-programmable flash