SCYD013 Search Results

sn74124

Abstract: logic diagram of 4bit binary ripple up counter SCYD013B LT 543 7-segment display datasheet sn 16862 4017-DECADE COUNTER 4511 logic diagram sn 16861 7404 hex inverter 741 1BX
Contextual Info: Digital Logic Pocket Data Book 2007 SLL SCYD013B Digital Logic Pocket Data Book IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries TI reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue

LT 543 7-segment display datasheet

Abstract: sn74124 4046 application note pll truth table of 4017 application note pll 4046 sn 74 als 324 LT 542 seven segment display data sheet 12a h3 sc sf PLL CD 4046 logic diagram of 4bit binary ripple up counter
Contextual Info: Digital Logic Pocket Data Book Pocket Data Book Digital Logic 2003 Printed in Japan 0103 SCYD013 2003 SLL Digital Logic Pocket Data Book 名称未設定-2 1 2003.1.14, 4:12 PM IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries TI reserve the right to make corrections, modifications,

CD4043BE HARRIS

Abstract: CD4043BE CD4043BEE4 d4043
Contextual Info: Data sheet acquired from Harris Semiconductor SCHS041D − Revised October 2003 The CD4043B and CD4044B types are supplied in 16-lead hermetic dual-in-line ceramic packages F3A suffix , 16-lead dual-in-line plastic packages (E suffix), 16-lead small-outline packages (D, DR, DT, DW, DWR,

hes 1-221

Contextual Info: SN54HC7002, SN74HC7002 QUADRUPLE POSITIVEĆNOR GATES WITH SCHMITTĆTRIGGER INPUTS SCLS033F − MARCH 1984 − REVISED NOVEMBER 2004 D D D D D D D Wide Operating Voltage Range of 2 V to 6 V Typical tpd = 14 ns Low Power Consumption, 20-µA Max ICC Low Input Current of 1 µA Max

Contextual Info: SN74LVC112A DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOP WITH CLEAR AND PRESET www.ti.com SCAS289L – JANUARY 1993 – REVISED AUGUST 2005 FEATURES • • • • • • • D, DB, DGV, NS, OR PW PACKAGE TOP VIEW Operates From 1.65 V to 3.6 V Inputs Accept Voltages to 5.5 V

Contextual Info: SN74LVC861A 10-BIT BUS TRANSCEIVER WITH 3-STATE OUTPUTS www.ti.com SCAS309I – MARCH 1993 – REVISED FEBRUARY 2005 FEATURES • • • • • • • • • Operates From 1.65 V to 3.6 V Inputs Accept Voltages to 5.5 V Max tpd of 6.4 ns at 3.3 V Typical VOLP Output Ground Bounce

Contextual Info: www.ti.com SN74ALVCH162260 12-BIT TO 24-BIT MULTIPLEXED D-TYPE LATCH WITH 3-STATE OUTPUTS SCAS570I – MARCH 1996 – REVISED AUGUST 2004 FEATURES • • • • • • • Member of the Texas Instruments Widebus Family EPIC™ Enhanced-Performance Implanted

cd4027b

Abstract: D4013 SB 125 024 CD4027BF3A real time application of D flip-flop
Contextual Info: Data sheet acquired from Harris Semiconductor SCHS032C − Revised October 2003 The CD4027B types are supplied in 16-lead hermetic dual-in-line ceramic packages F3A suffix , 16-lead dual-in-line plastic packages (E suffix), 16-lead small-outline packages (M, M96, MT, and NSR suffixes), and

Contextual Info: SN74ALS641A, SN74ALS642A, SN74AS641 OCTAL BUS TRANSCEIVERS WITH OPEN-COLLECTOR OUTPUTS SDAS300 – MARCH 1995 • DW OR N PACKAGE TOP VIEW Bidirectional Bus Transceivers in High-Density 20-Pin Packages Choice of True or Inverting Logic Package Options Include Plastic

SN-74LS153N

Abstract: SN74LS153N SN74LS153N texas
Contextual Info: PACKAGE OPTION ADDENDUM www.ti.com 26-Sep-2005 PACKAGING INFORMATION Orderable Device Status 1 Package Type Package Drawing Pins Package Eco Plan (2) Qty Lead/Ball Finish MSL Peak Temp (3) 76011012A ACTIVE LCCC FK 20 1 TBD Call TI Level-NC-NC-NC 7601101EA

SN74AUC2G125DCUR

Contextual Info: SN74AUC2G125 DUAL BUS BUFFER GATE WITH 3-STATE OUTPUTS www.ti.com SCES532A – DECEMBER 2003 – REVISED MARCH 2005 FEATURES • • • • • • • • • DCT OR DCU PACKAGE TOP VIEW Available in the Texas Instruments NanoStar and NanoFree™ Packages

Contextual Info: SN54ABT823, SN74ABT823 9-BIT BUS-INTERFACE FLIP-FLOPS WITH 3-STATE OUTPUTS SCBS158E – JANUARY 1991 – REVISED MAY 1997 D D D D D D SN54ABT823 . . . JT OR W PACKAGE SN74ABT823 . . . DB, DW, OR NT PACKAGE TOP VIEW OE 1D 2D 3D 4D 5D 6D 7D 8D 9D CLR GND These 9-bit flip-flops feature 3-state outputs

SN74AVC

Abstract: SN74AVC "cross-reference"
Contextual Info: SN74AVC16646 16-BIT BUS TRANSCEIVER AND REGISTER WITH 3-STATE OUTPUTS www.ti.com SCES181F – DECEMBER 1998 – REVISED JUNE 2005 • FEATURES • • • • Member of the Texas Instruments Widebus Family EPIC™ Enhanced-Performance Implanted CMOS Submicron Process

Contextual Info: Data sheet acquired from Harris Semiconductor SCHS059C – Revised September 2003 The CD4078B types are supplied in 14-lead hermetic dual-in-line ceramic packages F3A suffix , 14-lead dual-in-line plastic packages (E suffix), 14-lead small-outline packages (M, MT, M96, and NSR suffixes),

D4013B

Abstract: cd4013be D4013
Contextual Info: Data sheet acquired from Harris Semiconductor SCHS023D − Revised April 2005 The CD4013B types are supplied in 14-lead hermetic dual-in-line ceramic packages F3A suffix , 14-lead dual-in-line plastic packages (E suffix), 14-lead small-outline packages (M, MT, M96, and NSR suffixes),

CANBUS-DEMO

Contextual Info: SN74AHCT1G126 SINGLE BUS BUFFER GATE WITH 3-STATE OUTPUT SCLS380I – AUGUST 1997 – REVISED JANUARY 2003 D D D D D D D DBV OR DCK PACKAGE TOP VIEW Operating Range of 4.5 V to 5.5 V Max tpd of 6 ns at 5 V Low Power Consumption, 10-µA Max ICC ±8-mA Output Drive at 5 V

OF946

Contextual Info: 1CY74FCT16444T/2 H244T Data sheet acquired from Cypress Semiconductor Corporation. Data sheet modified to remove devices not offered. CY74FCT16244T CY74FCT162244T CY74FCT162H244T 16-Bit Buffers/Line Drivers SCCS028B - December 1987 - Revised September 2001

Contextual Info: SN74GTLPH1645 16-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVER www.ti.com FEATURES • • • • • • • • • • • • Member of the Texas Instruments Widebus Family TI-OPC™ Circuitry Limits Ringing on Unevenly Loaded Backplanes OEC™ Circuitry Improves Signal Integrity and

military radar 20 pages documentation

Contextual Info: SN74LVTH244AĆEP 3.3ĆV ABT OCTAL BUFFER/DRIVER WITH 3ĆSTATE OUTPUTS SCAS691C − APRIL 2003 − REVISED OCTOBER 2003 D Controlled Baseline D D D D D D D D D Bus Hold on Data Inputs Eliminates the − One Assembly/Test Site, One Fabrication Site Extended Temperature Performance of

SN74LS373N

Abstract: sn74ls373p
Contextual Info: SN54LS373, SN54LS374, SN54S373, SN54S374, SN74LS373, SN74LS374, SN74S373, SN74S374 OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS SDLS165B – OCTOBER 1975 – REVISED AUGUST 2002 D D D D D D Choice of Eight Latches or Eight D-Type Flip-Flops in a Single Package

Contextual Info: SN74LVCZ240A OCTAL BUFFER/DRIVER WITH 3-STATE OUTPUTS www.ti.com SCES273H – JUNE 1999 – REVISED APRIL 2005 FEATURES • • • • • • • • • DB, DGV, DW, N, NS, OR PW PACKAGE TOP VIEW Operates From 2.7 V to 3.6 V Inputs Accept Voltages to 5.5 V

Contextual Info: SN74LVCH16540A 16-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS www.ti.com SCAS569H – MARCH 1996 – REVISED MARCH 2005 FEATURES • • • • • • • • • • • DGG, DGV, OR DL PACKAGE TOP VIEW Member of the Texas Instruments Widebus Family Operates From 1.65 V to 3.6 V

Contextual Info: SN74ALVCH162374 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS www.ti.com SCES092F – JANUARY 1997 – REVISED OCTOBER 2004 FEATURES • • • • • DGG OR DL PACKAGE TOP VIEW Member of the Texas Instruments Widebus Family Bus Hold on Data Inputs Eliminates the Need

Contextual Info: Data sheet acquired from Cypress Semiconductor Corporation. Data sheet modified to remove devices not offered. CY74FCT16841T CY74FCT162841T 20-Bit Latches SCCS067A - July 1994 - Revised October 2001 Features • • • • • • • • Functional Description