RGB526DB Search Results

B60V

Contextual Info: RGB526/RGB526DB 5.0 5.1 VRAM Pixel Formats 5.3 Bit Ordering With 4 BPP format 8 pixels 32 bit VRAM width or 16 pixels (64 bit VRAM width) are obtained for each pixel port data access. As noted above the default access of the two pixels within each byte are high-to-low:

Contextual Info: RGB526/RGB526DB 13.0 Pin Descriptions Table 11. Pin Descriptions Signal ¡1 1 1 1 Description xxiÊxxx REFCLK I 80 FS[1:0] I 96,83 DDOTCLK o 116 SCLK 113 LCLK I 109 SYSCLK o 75 PIX[63:0] I 10 «1ft *7 66,65,64, ÎP3 1.22 121320.119,118, 117 140.139,138,137,136,

0X0009

Abstract: 0x0070
Contextual Info: RGB526/RGB526DB Table 10. Internal Register Sum m ary Continued 11.0 Internal Register - Summary R S[2:0] Index R/W R eset V alue 110 0x0015 y 0x08 SY SCLK N (Sy stem P L L Reference D ivider) 110 0x0016 y 0x41 SY SCLKM (Sy stem P L L VCO D ivider) 110 0x0017

RGB524

Abstract: RGB526/RGB526DB
Contextual Info: RGB526/RGB526DB 1.0 Microprocessor Access As seen on th e m icroprocessor bus th e re are eight I/O addresses, selected by RS[2:0]. Two indirect schemes are used to access all of th e in te rn a l registers and arrays through th ese eight prim ary I/O addresses.

RS-343-A

Abstract: RS-343A
Contextual Info: RGB526/RGB526DB 15.0 Video Waveforms WHITE BLACK BLANK SYNC Table 17. Composite Video Output Waveform D o u b ly te r m in a t e d 75 o h m s, R R E F = 698 o h m s Sync No No Y es P ed esta l No Y es No V a lu e IR E WHITE mA V 18.65 0.70 100 mA V 19.05 0.714

Contextual Info: RGB526/RGB526DB 1.0 Microprocessor Access As seen on the m icroprocessor bus there are eight I/O addresses, selected by RS[2:0]. Two indirect schem es are used to access all of the internal registers and arrays through th ese eight prim ary I/O addresses.

Contextual Info: RGB526/RGB526DB 18.0 Change Summary Table 20. Summary of Changes Date Changes 04/17/95 1. 09/25/95 This revision adds the RGB526DB product; the document becomes a combined RGB526/RGB526DB data sheet. All of the changes are related to adding the RGB526DB product information:

Contextual Info: RGB526/RGB526DB N gives finer control in program m ing for the desired output frequencies, and allows the in ternal operat­ ing points of the P L L s to be fine tuned. Appendix A.O RGB526, RGB526DB Comparison The R G B 526D B is a su perset of th e R G B 526 th a t adds

37RGB526

Contextual Info: RGB526/RGB526DB 12.0 Register Descriptions 12.1 Pixel Mask Direct Access Registers T h e d irec t access re g iste rs a re a d d re ssed u sin g RS[2:0] in p u ts. RS[2:0]: 010 Access: R ead /W rite Power on Value: U n d efin ed Palette Address Write Mode

s26d

Contextual Info: RGB526/RGB526DB 3.0 Modes of Operation Pixel d ata can come from the VGA port or the VRAM pixel port, a s selected by the PO R T S E L b it of the M is­ cellaneous Control 2 register. I f the VRAM pixel port is selected, the pixel form at can be 4 B P P bits p er pixel , 8 BPP, 15/16 BPP, 24 B P P

d2222

Contextual Info: RGB526/RGB526DB C.O R EF DIV COUNT R eferen ce D iv id e C ount This num ber provides a count value for dividing down th e incoming REFCLK. It m u st be betw een 2 and 31. O peration of th e PLL is indeterm inate if th is num ber is 0 or 1. PLL Compatibility

0x0016

Contextual Info: RGB526/RGB526DB 2.0 Clocking 2.1 Clock Generators There are two on-board clock generators: pixel clock and system clock SYSCLK . Each clock generator uses a sep arate program m able phase locked loop (PLL). This causes th e SYSCLK s ta rt up frequency to be

VRAM

Contextual Info: RGB526/RGB526DB D.O Switching Into VGA Mode The R G B 526/R G B 526D B h a s two fun d am en tal m odes of operation which depend on the in pu t pixel port selected, VGA or VRAM. The port is selected with the “PO RT S E L ” bit bit 0 of M iscellan eous Control 2 register.

Contextual Info: RGB526/RGB526DB 14.0 Electrical and Timing Specifications Table 13. Recommended Operating Conditions 170 M Hz P a ra m e te r 220 M H z Sym bol P ow er Supply U n its VDD, DACVDD, PLLVDD C a se T e m p e ra tu re M in. M ax. M in. M ax. 3.0 3.6 3.0 3.6 Volts

Contextual Info: RGB526/RGB526DB 6.0 Controls 6.1 Blank and Border Control The B L A N K and B O R D ER /O E sig n als control the w ay in which d a ta is p resented to the DACs. T hese control sig n als are u sed to determ ine when pixel d ata is valid, when the border color is to be displayed, where the cur­

Contextual Info: RGB526/RGB526DB 9.0 Power Management T h e follow ing re g iste rs a re u se d to control pow er d issi­ p atio n : 9.1 □ P ow er M a n a g e m e n t index 0x0005 □ M iscellaneous Clock C ontrol (index 0x0002) □ Sync C ontrol (index 0x0003) □ M iscellaneous C ontrol 1 (index 0x0070)

Contextual Info: RGB624/RGB624DB 1.0 Microprocessor Access As seen on th e m icroprocessor bus th e re are eight I/O addresses, selected by RS[2:0]. Two indirect schemes are used to access all of th e in te rn a l registers and arrays through th ese eight prim ary I/O addresses.

Contextual Info: RGB624/RGB624DB Appendix A.O RGB624, RGB624DB Comparison T h e R G B 6 2 4 D B is a s u p e r s e t o f th e R G B 6 2 4 t h a t a d d s th e 16 B P P d o u b le b u ffe r o p e ra tio n . T h e tw o p ro d u c ts a re p in a n d re g is te r c o m p a tib le a n d a re id e n tic a l in a ll

RGB624

Abstract: cursor
Contextual Info: RGB624/RGB624DB 9.0 Controls 9.1 Blank and Border Control The B L A N K and B O R DER/O E signals control the way in which data is presented to the DACs. These control signals are used to determ ine when pixel data is valid, when the border color is to be displayed, where the cur­