RGB624DB Search Results

Contextual Info: RGB624/RGB624DB 1.0 Microprocessor Access As seen on th e m icroprocessor bus th e re are eight I/O addresses, selected by RS[2:0]. Two indirect schemes are used to access all of th e in te rn a l registers and arrays through th ese eight prim ary I/O addresses.

a6ke

Abstract: a40V c2bl B60V coy 11
Contextual Info: RGB624/RGB624DB 6.0 6 Bit Linear Palette Output The 6 B IT LI N 6 bit linear b it of the Palette Control register affects the form at of RGB color data read from the palettes and presented to the DACs in indirect color mode. It only has effect when th e color resolution is set

Contextual Info: RGB624/RGB624DB Appendix A.O RGB624, RGB624DB Comparison T h e R G B 6 2 4 D B is a s u p e r s e t o f th e R G B 6 2 4 t h a t a d d s th e 16 B P P d o u b le b u ffe r o p e ra tio n . T h e tw o p ro d u c ts a re p in a n d re g is te r c o m p a tib le a n d a re id e n tic a l in a ll

CAPACITOR 64 680 4J

Abstract: CAPACITOR 62 680 4J PIX203 IX533 RGB624
Contextual Info: RGB624/RGB624DB 16.0 Pin Descriptions Table 16. Pin Descriptions Signal Typ e D escription Pin s Clocks and Clock Controls REFC LK 1 80 Reference Clock. A fixed frequency of 2 M H z to 100 M Hz applied to th is pin provides the reference clock for the programmable pixel and system clock

0X0047

Abstract: RGB624 GMPM2-B112RCBSXU.110
Contextual Info: RGB624/RGB624DB 14.0 Internal Register - Summary RS[2:0] Index R /W Reset Value 110 0x0015 / 0x08 SYSCLKN S ystem P L L Reference D iv id e r 110 0x0016 / 0x41 SYSCLK M (S ystem P L L VCO D iv id e r) 110 0x0017 110 0x0018 R egister Nam e 110 0x00190x001f

RGB624

Abstract: cursor
Contextual Info: RGB624/RGB624DB 9.0 Controls 9.1 Blank and Border Control The B L A N K and B O R DER/O E signals control the way in which data is presented to the DACs. These control signals are used to determ ine when pixel data is valid, when the border color is to be displayed, where the cur­

37RGB624cf

Abstract: RGB624 37RGB624
Contextual Info: RGB624/RGB624DB 19.0 Package Information % 20.0 Ordering Information Table 24. Part Numbers Product Part Number Speed IBM 37RGB624 CF 17 170 MHz IBM 37RGB624 CF 22 220 MHz IBM 37RGB624 DB 17 170 MHz IBM 37RGB624 DB 22 220 MHz RGB624 RGB624DB October 9 , 1995

RGB624

Contextual Info: RGB624/RGB624DB 7.0 Color Space Conversion The internal color space converter takes pixels with Y, U, and V values of 8 bits each and converts them to pix­ els of R, G, and B values of 8 bits each, using the follow­ ing equations: 7.2 Coefficients The constants K1 - K4 are 8 bit values are can be pro­

FS10J

Contextual Info: RGB624/RGB624DB 15.0 Register Descriptions Pixel Mask / 15.1 7 6 The direct access registers are addressed using RS 2:0] inputs. RS[2:0]: 010 Access: Read/Write Bits 7 - 0 6 5 4 3 2 1 0 > W R IT E A d dress RS[2:0]: 000 Access: Read/Write Pow er on Value: Undefined

b624

Contextual Info: RGB624/RGB624DB 21.0 Change Summary _ Table 25. Summary of Changes Date Changes 02/06/95 1. 10/09/95 T h is re visio n adds th e R G B 624D B p ro d u ct; th e d o cu m e n t becomes a co m b in e d R G B 624/R G B 624D B d a ta

DF0001

Abstract: RGB624
Contextual Info: RGB624/RGB624DB D.O PLL Compatibility Programming REF DIV COUNT R e fe re n c e D ivide C o u n t This The RG B51x and RGB52x products all have a program­ mable P L L for generating a pixel clock, and the RG B524 and RG B528 have a second P L L for driving a "S Y S C L K "

Contextual Info: RGB624/RGB624DB 12.0 Power Management 12.3 The following registers are used to control power dissipation: Most of the digital logic power dissipation occurs as a result of clocking. The IC L K PWR, SCLK PWR, D D O T PWR, and S YN C PW R bits of the Power Management

RGB624

Contextual Info: RGB624/RGB624DB E.O Switching Into VGA Mode The R G B624/RGB624DB has two fundam ental modes of operation which depend on the input pixel port selected, VGA or V R A M . The port is selected w ith the "PORT SEL” b it bit 0 of Miscellaneous Control 2 register.

Contextual Info: RGB624/RGB624DB 8.0 Sub-sampled Chrominance Issues 8.3 W ith m ixed Y U / V and R G B pixels, the requirem ent that the Y U / V pixels occur in p a irs also, in effect, requires th at the R G B pixels occur in p a irs and that the p airs be aligned on even pixel boundaries. If th is condition is vio­

RGB624

Contextual Info: RGB624/RGB624DB 17.0 Electrical and Timing Specifications Table 18. Recommended Operating Conditions 170 M H z P aram eter 220 M H z Symbol U n its M in . M ax. M in . M ax . VDD, DACVDD, PLLVDD 3.0 3.6 3.0 3.6 Volts Case Temperature TC 100 100 C DAC Output Load

RGB624

Abstract: C2-M3
Contextual Info: RGB624/RGB624DB 2.0 Clocking 2.1 Clock Generators T h ere are tw o on-board clock generators: p ixe l clock and system clock SYSC LK . Each clock g e n e ra to r uses a separate p ro gram m able phase locked loop (P LL). T h is causes th e S Y S C LK s ta rt up frequency to be

RS-343-A

Abstract: ef927 RS-343A RGB624
Contextual Info: RGB624/RGB624DB 18.0 Video Waveforms WHITE BLACK BLANK SYNC Table 22. Composite Video Output Waveform D o u b ly te rm in a te d 75 ohms, R R E F= 698 ohm s Sync No Pedestal V alu e No No IR E W H ITE Yes Yes mA V 18.65 0.70 100 IR E i No mA V 19.05 0.714

PIX-1400

Contextual Info: RGB624/RGB624DB 3.0 Modes of Operation Pixel data can come from the V G A port or the VRAM pixel port, as selected by the P O R T S E L bit of the M is­ cellaneous Control 2 register. If the V R A M pixel port is selected, the pixel format can be 4 B P P bits per pixel , 8 BPP, 15/16 BPP, 24 B P P