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    Untitled

    Abstract: No abstract text available
    Text: CTS100EL16 LVPECL Oscillator Gain Stage & Buffer with Enable MLP8, MSOP8, MSOP10 Features      Block Diagram 250ps Propagation Delay High Voltage Gain vs. Standard EL16 75k Enable Pull-down Resistor High Bandwidth for 1GHz -147 dBc/Hz Typical Noise Floor


    Original     		CTS100EL16 MSOP10 250ps CTS100EL16 CTS100EL16VOUG MSOP10) CTS100EL16VONG CTS100EL16VOTG PDF

    Untitled

    Abstract: No abstract text available
    Text: CTSLV394 LVPECL Divide by 1, Divide by 2 Clock Generator w/ Tri-State Compatible Outputs MLP8 Features          Block Diagram Selectable Divide Ratio Selectable Enable Priority and Threshold CMOS or PECL Tristate Compatible Outputs


    Original     		CTSLV394 -145dBc/Hz -151dBc/Hz CTSLV394 CTSLV394NG RevA1113 PDF

    SON8

    Abstract: No abstract text available
    Text: CTSLV363 Low Phase Noise LVPECL Buffer and Translator SON8 Features Block Diagram LVPECL Outputs Optimized for Very Low Phase Noise -165dBc/Hz  Up to 1GHz Bandwidth  Selectable ÷1, ÷2 Output  Selectable Enable Logic  3.0V to 3.6V Operation


    Original     		CTSLV363 -165dBc/Hz) CTSLV363 CTSLV363QG RevA1113 SON8 PDF

    Untitled

    Abstract: No abstract text available
    Text: CTSLV392 LVPECL Divide by 1, Divide by 2 Clock Generator w/ Selectable Enable MLP8 Features        Block Diagram Selectable Divide Ratio Selectable Enable Priority and Threshold CMOS or PECL 3.0V to 5.5V Power Supply -145dBc/Hz (÷1) Typical Noise Floor


    Original     		CTSLV392 -145dBc/Hz -151dBc/Hz CTSLV392 CTSLV392NG RevA1113 PDF

    Untitled

    Abstract: No abstract text available
    Text: CTS100ELT23 Dual Differential PECL to CMOS/TTL Translator MSOP8, SOIC8 Features Block Diagram   3.5ns Typical Propagation Delay <500ps Typical Output to Output Skew  Differential PECL Inputs  Flow Through Pinouts  CMOS/TTL Outputs  RoHS Compliant Pb Free Packages


    Original     		CTS100ELT23 500ps CTS100ELT23 MC100ELT23. RevA1113 CTS100ELT23DG PDF

    QFN8

    Abstract: No abstract text available
    Text: CTSLV353 Low Phase Noise LVPECL Buffer and Translator QFN8, SON8 Features Block Diagram LVPECL Outputs Optimized for Very Low Phase Noise -165dBc/Hz  Up to 800MHz Bandwidth  Selectable ÷1, ÷2 Output  Selectable Enable Logic  3.0V to 3.6V Operation


    Original     		CTSLV353 -165dBc/Hz) 800MHz CTSLV353 165dBc/Hz) CTSLV363. RevA1113 QFN8 PDF

    Untitled

    Abstract: No abstract text available
    Text: CTSLVEL16VT PECL/ECL Oscillator Gain Stage & Buffer with Selectable Enable MLP8 Block Diagram Features     Minimizes External Components High Bandwidth for 1GHz Similar Operation as CTSLVEL16VR Except in Disabled Condition QHG is High -147 dBc/Hz Typical Noise Floor


    Original     		CTSLVEL16VT CTSLVEL16VR CTSLVEL16VT CTSLVEL16VTNNG RevA1113 PDF

    marking+3610

    Abstract: No abstract text available
    Text: CTSLVEL16VV Dual Frequency PECL/ECL Oscillator Gain Stage & Buffer with Enable MLP16 Features     Block Diagram Minimizes External Components Similar Operation as CTSLVEL16VR except with Selectable Data Input Pairs High Bandwidth for 1GHz -147 dBc/Hz Typical Noise Floor


    Original     		CTSLVEL16VV MLP16 CTSLVEL16VR CTSLVEL16VV CTSLVEL16 RevA1113 CTSLVEL16VVRLG marking+3610 PDF

    Untitled

    Abstract: No abstract text available
    Text: CTS100LVEL58 LVPECL 2:1 Multiplexer MLP8, MSOP8, SOIC8 Features       Block Diagram 440ps Propagation Delay  Operating Voltage of 3.0 to 5.5V Internal Input Pull-down Resistors Direct Replacement for ON Semi MC100LVEL58 ROHS Compliant Pb Free Packages


    Original     		CTS100LVEL58 440ps MC100LVEL58 CTS100LVEL58 CTS100EL58. CTS100EL58 LVEL58 MC100LVEL58. FunctionalitTS100LVEL58 PDF

    CTS10

    Abstract: No abstract text available
    Text: CTS10EL89 PECL/ECL Coaxial Cable Driver SOIC8 Features  Block Diagram Direct Replacement for ON Semi MC10EL89  1.6V Output Swing  375ps Propagation Delay  Internal Input Pull-down Resistors  RoHS Compliant Pb Free Packages  Description


    Original     		CTS10EL89 MC10EL89 375ps CTS10EL89 RevA1113 CTS10EL89DG CTS10 PDF

    Untitled

    Abstract: No abstract text available
    Text: CTSLVEL16VR PECL/ECL Oscillator Gain Stage & Buffer with Selectable Enable MLP8, MLP16 Features      Block Diagram Minimizes External Components Selectable Enable Polarity and Threshold CMOS or PECL High Bandwidth for 1GHz Similar Operation as CTS100EL16


    Original     		CTSLVEL16VR MLP16 CTS100EL16 CTSLVEL16VR CTSLVEL16VRNNG CTSLVEL16VRLG CTSLVEL16VRNEG RevA1113 PDF

    Untitled

    Abstract: No abstract text available
    Text: CTST571 Programmable Capacitive Tuning IC SON8, MLP6 Block Diagram Features       Capacitive Tuning Range of 6.6pF to 37.553pF 0.063pF Minimum Step Size Continually Programmable with Register or EEPROM Data Storage May Be Placed in Parallel for Greater


    Original     		CTST571 553pF 063pF CTST571 RevA1113 CTST571QG PDF

    Untitled

    Abstract: No abstract text available
    Text: CTSLV310 Ultra-Low Phase Noise LVPECL, LVDS Buffer and Translator SON8, MSOP8 Features Block Diagram 2.5V-3.3V Operation Ultra-Low Phase Noise Floor • LVPECL -167dBc/Hz  LVDS -165dBc/Hz  Configurable  LVPECL or LVDS Output  ÷1 or ÷2  Enable Active High or Low


    Original     		CTSLV310 -167dBc/Hz -165dBc/Hz CTSLV310 CTSLV315. CTSLV31le CTSLV310QG CTSLV310TG RevA1113 PDF

    Untitled

    Abstract: No abstract text available
    Text: CTSLV351 Low Phase Noise LVPECL Buffer & Translator SC70-6 Features Block Diagram LVPECL Outputs Optimized for Very Low Phase Noise -165dBc/Hz  Up to 800MHz Bandwidth  Selectable ÷1, ÷2 Output  Selectable Enable Logic  3.0V to 3.6V Operation


    Original     		CTSLV351 SC70-6 -165dBc/Hz) 800MHz CTSLV351 CTSLV353 CTSLV351SG PDF

    Untitled

    Abstract: No abstract text available
    Text: CTS100ELT22 Dual CMOS/TTL to Differential PECL Translator MSOP8, SOIC8 Block Diagram Features      0.5ns Typical Propogation Delay <100ps Typical Output to Output Skew Flow Through Pinouts Differential PECL Output RoHS Compliant Pb Free Packages


    Original     		CTS100ELT22 100ps CTS100ELT22 MC100ELT22, MC100LVELT22 SY89322V. RevA1113 PDF

    Untitled

    Abstract: No abstract text available
    Text: CTS100LVEL11 LVPECL 1:2 Differential Fan-out Buffer MLP8, MSOP8, SOIC8 Features Block Diagram 265ps Propagation Delay 5ps Skew Between Outputs Internal Input Pull-Down Resistors Direct Replace for ON Semi MC100LVEL11 and MC100EL11  RoHS Compliant Pb Free Packages


    Original     		CTS100LVEL11 265ps MC100LVEL11 MC100EL11 CTS100LVEL11 RevA1113 CTS100LVEL11NG PDF

    Untitled

    Abstract: No abstract text available
    Text: CTSLV315 Ultra-Low Phase Noise LVPECL, LVDS Buffer and Translator with Gain SON8, MSOP8 Features Block Diagram 2.5V-3.3V Operation Ultra-Low Phase Noise Floor • LVPECL -167dBc/Hz  LVDS -165dBc/Hz  Configurable  LVPECL or LVDS Output  ÷1 or ÷2


    Original     		CTSLV315 -167dBc/Hz -165dBc/Hz CTSLV315 CTSLV315QG CTSLV315TG RevA1113 PDF