CTSLVEL16 Search Results

CTSLVEL16 Datasheets (4)

Part	ECAD Model	Manufacturer	Description	Curated	Datasheet Type	PDF
CTSLVEL16VRNLG		CTS	Interface - Signal Buffers, Repeaters, Splitters, Integrated Circuits (ICs), LVPECL OSC GAIN STAGE & BUFFER		Original	PDF
CTSLVEL16VRNNG		CTS	Interface - Signal Buffers, Repeaters, Splitters, Integrated Circuits (ICs), LVPECL OSC GAIN STAGE & BUFFER		Original	PDF
CTSLVEL16VTNNG		CTS	Interface - Signal Buffers, Repeaters, Splitters, Integrated Circuits (ICs), LVPECL OSC GAIN STAGE & BUFFER		Original	PDF
CTSLVEL16VVRLG		CTS	Interface - Signal Buffers, Repeaters, Splitters, Integrated Circuits (ICs), LVPECL OSC GAIN STAGE & BUFFER		Original	PDF

CTSLVEL16 Datasheets Context Search

Catalog Datasheet	MFG & Type	PDF	Document Tags
Untitled Abstract: No abstract text available Text: CTSLVEL16VT PECL/ECL Oscillator Gain Stage & Buffer with Selectable Enable MLP8 Block Diagram Features     Minimizes External Components High Bandwidth for 1GHz Similar Operation as CTSLVEL16VR Except in Disabled Condition QHG is High -147 dBc/Hz Typical Noise Floor	Original	PDF	CTSLVEL16VT CTSLVEL16VR CTSLVEL16VT CTSLVEL16VTNNG RevA1113
Untitled Abstract: No abstract text available Text: CTSLVEL16VR PECL/ECL Oscillator Gain Stage & Buffer with Selectable Enable MLP8, MLP16 Features      Block Diagram Minimizes External Components Selectable Enable Polarity and Threshold CMOS or PECL High Bandwidth for 1GHz Similar Operation as CTS100EL16	Original	PDF	CTSLVEL16VR MLP16 CTS100EL16 CTSLVEL16VR CTSLVEL16VRNNG CTSLVEL16VRNLG RevB0114
marking+3610 Abstract: No abstract text available Text: CTSLVEL16VV Dual Frequency PECL/ECL Oscillator Gain Stage & Buffer with Enable MLP16 Features     Block Diagram Minimizes External Components Similar Operation as CTSLVEL16VR except with Selectable Data Input Pairs High Bandwidth for 1GHz -147 dBc/Hz Typical Noise Floor	Original	PDF	CTSLVEL16VV MLP16 CTSLVEL16VR CTSLVEL16VV CTSLVEL16 RevA1113 CTSLVEL16VVRLG marking+3610
Untitled Abstract: No abstract text available Text: CTSLVEL16VR PECL/ECL Oscillator Gain Stage & Buffer with Selectable Enable MLP8, MLP16 Features      Block Diagram Minimizes External Components Selectable Enable Polarity and Threshold CMOS or PECL High Bandwidth for 1GHz Similar Operation as CTS100EL16	Original	PDF	CTSLVEL16VR MLP16 CTS100EL16 CTSLVEL16VR CTSLVEL16VRNNG CTSLVEL16VRLG CTSLVEL16VRNEG RevA1113