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    QUAD TWO INPUT NAND SCHMITT TRIGGER LOW POWER Search Results

    QUAD TWO INPUT NAND SCHMITT TRIGGER LOW POWER Result Highlights (5)

    Part ECAD Model Manufacturer Description Download Buy
    MHM411-21 Murata Manufacturing Co Ltd Ionizer Module, 100-120VAC-input, Negative Ion Visit Murata Manufacturing Co Ltd
    MGN1S1208MC-R7 Murata Manufacturing Co Ltd DC-DC 1W SM 12-8V GAN Visit Murata Manufacturing Co Ltd
    MGN1D120603MC-R7 Murata Manufacturing Co Ltd DC-DC 1W SM 12-6/-3V GAN Visit Murata Manufacturing Co Ltd
    MGN1S1212MC-R7 Murata Manufacturing Co Ltd DC-DC 1W SM 12-12V GAN Visit Murata Manufacturing Co Ltd
    MGN1S0508MC-R7 Murata Manufacturing Co Ltd DC-DC 1W SM 5-8V GAN Visit Murata Manufacturing Co Ltd

    QUAD TWO INPUT NAND SCHMITT TRIGGER LOW POWER Datasheets Context Search

    Catalog Datasheet MFG & Type Document Tags PDF

    TTL Schmitt-Trigger LOW POWER SCHOTTKY

    Abstract: 74HC132 74VHC132 74VHC132M 74VHC132MTC 74VHC132SJ M14A M14D MTC14 VHC00
    Text: 74VHC132 Quad 2-Input NAND Schmitt Trigger Features General Description • High Speed: tPD = 3.9ns Typ. at VCC = 5V ■ Power down protection is provided on all inputs The VHC132 is an advanced high speed CMOS 2-input NAND Schmitt Trigger Gate fabricated with silicon gate


    Original     		74VHC132 VHC132 VHC00 74VHC132 TTL Schmitt-Trigger LOW POWER SCHOTTKY 74HC132 74VHC132M 74VHC132MTC 74VHC132SJ M14A M14D MTC14 PDF

    74LVC132A

    Abstract: 74LVC132ABQ 74LVC132AD 74LVC132APW TSSOP14
    Text: 74LVC132A Quad 2-input NAND Schmitt trigger Rev. 01 — 15 December 2006 Product data sheet 1. General description The 74LVC132A is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families. The 74LVC132A provides four 2-input NAND gates with Schmitt trigger inputs. It is


    Original     		74LVC132A 74LVC132A 74LVC132ABQ 74LVC132AD 74LVC132APW TSSOP14 PDF

    3 to 8 bit decoder vhdl IEEE format

    Abstract: ATL60 ATLS60 PO61 ttl buffer
    Text: ATL60 Features x x x x x x x x 0.6Pm Drawn Gate Length 0.5Pm Leff Sea-of-Gates Architecture With Triple Level Metal 5.0 Volt, 3.3 Volt, and 2.0 Volt Operation Including Mixed Voltages On Chip Phase Locked Loop Available to Synthesize Frequencies up to 150 MHz and Manage Chip-to-Chip Clock Skew


    Original     		ATL60 ATL60 3 to 8 bit decoder vhdl IEEE format ATLS60 PO61 ttl buffer PDF

    PO61

    Abstract: ATMEL 340 atmel 424 ATLS60 ATL60 ttl buffer 3.6v Tri-State Buffer bga ambit inverter circuit AOI222 ATMEL 218
    Text: Features • • • • • • • • 0.6 µm Drawn Gate Length 0.5 µm Leff Sea-of-Gates Architecture with Triple Level Metal 5.0V, 3.3V and 2.0V Operation including Mixed Voltages On-chip Phase Locked Loop Available to Synthesize Frequencies up to 150 MHz and


    Original     		ATL60 0388C 11/99/xM PO61 ATMEL 340 atmel 424 ATLS60 ttl buffer 3.6v Tri-State Buffer bga ambit inverter circuit AOI222 ATMEL 218 PDF

    HEF4093BP

    Abstract: HEF4093BP datasheet free download HEF4093BT HEF4093B MO-001
    Text: HEF4093B Quad 2-input NAND Schmitt trigger Rev. 05 — 28 July 2009 Product data sheet 1. General description The HEF4093B is a quad two-input NAND gate. Each input has a Schmitt trigger circuit. The gate switches at different points for positive-going and negative-going signals. The


    Original     		HEF4093B HEF4093B HEF4093BP HEF4093BP datasheet free download HEF4093BT MO-001 PDF

    HEF4093BP

    Abstract: HEF4093BT NXP HEF4093BT MO-001 HEF4093B JESD22-A114E
    Text: HEF4093B Quad 2-input NAND Schmitt trigger Rev. 04 — 12 June 2008 Product data sheet 1. General description The HEF4093B is a quad two-input NAND gate. Each input has a Schmitt trigger circuit. The gate switches at different points for positive-going and negative-going signals. The


    Original     		HEF4093B HEF4093B HEF4093BP HEF4093BT NXP HEF4093BT MO-001 JESD22-A114E PDF

    atmel 952

    Abstract: atmel h 952 ATL35 vhdl code for flip-flop jk flip flop to d flip flop conversion RTL 204 605 vhdl code for D Flipflop dssb oak dsp AOI222
    Text: Features • High Speed - 150 ps Gate Delay - 2 input NAND, FO=2 nominal • Up to 3.7 Million Used Gates and 976 Pins • System Level Integration Technology ™ ARM7TDMI and AVR RISC Microcontrollers, OakDSP™ and Lode™DSP Cores, 10T/100 Ethernet MAC, USB and PCI Cores,


    Original     		10T/100 ATL35 atmel 952 atmel h 952 vhdl code for flip-flop jk flip flop to d flip flop conversion RTL 204 605 vhdl code for D Flipflop dssb oak dsp AOI222 PDF

    HEF4093BP

    Abstract: HEF4093BP free HEF4093BT aSTABLE MULTIVIBRATORS WITH SCHMITT-TRIGGER IN HEF4093BP datasheet free download HEF4093B MO-001 HEF4093 HEF40 Multivibrators
    Text: HEF4093B Quad 2-input NAND Schmitt trigger Rev. 7 — 1 September 2010 Product data sheet 1. General description The HEF4093B is a quad two-input NAND gate. Each input has a Schmitt trigger circuit. The gate switches at different points for positive-going and negative-going signals. The


    Original     		HEF4093B HEF4093B HEF4093BP HEF4093BP free HEF4093BT aSTABLE MULTIVIBRATORS WITH SCHMITT-TRIGGER IN HEF4093BP datasheet free download MO-001 HEF4093 HEF40 Multivibrators PDF

    atmel 424

    Abstract: AMBIT inverter atmel 545 ATMEL 340 crystal oscillator buffer Structure of D flip-flop DFFSR s051 crystal OAI222 CMOS Transmission gate Specifications Tri-State Buffer CMOS
    Text: Features • 0.5 µm Drawn Gate Length 0.45µm Leff Sea-of-Gates Architecture With Triple Level Metal • 3.3V Operation • 5.0V Compatible Input Buffers • On-chip Phase Locked Loop (PLL) Available to Synthesize Frequencies up to 150 MHz • • • •


    Original     		ATL50 0753B 11/99/xM atmel 424 AMBIT inverter atmel 545 ATMEL 340 crystal oscillator buffer Structure of D flip-flop DFFSR s051 crystal OAI222 CMOS Transmission gate Specifications Tri-State Buffer CMOS PDF

    74HC132

    Abstract: 74VHC132 74VHC132M 74VHC132MTC 74VHC132N 74VHC132SJ M14A M14D VHC00 VHC132
    Text: 74VHC132 Quad 2-Input NAND Schmitt Trigger General Description The VHC132 is an advanced high speed CMOS 2-input NAND Schmitt Trigger Gate fabricated with silicon gate CMOS technology. It achieves the high-speed operation similar to Bipolar Schottky TTL while maintaining the CMOS


    Original     		74VHC132 VHC132 VHC00 74HC132 74VHC132 74VHC132M 74VHC132MTC 74VHC132N 74VHC132SJ M14A M14D PDF

    74ALS283

    Abstract: 74ALS148 74ALS194 0-99 counter by using 4 dual jk flip flop 004887 ATL60 TTL109 TTL138 TTL139 TTL148
    Text: Cell Library Index How to Use This Cell Library Index The cell index contains the macro cell’s timing, size and loading information. The data included in the cell timing information is explained in detail below. Cell Parameters Sites: Lists the number of gate array cell sites the macrocell occupies. This can be


    Original     		ATL50 ATL60 DP32x36) 74ALS283 74ALS148 74ALS194 0-99 counter by using 4 dual jk flip flop 004887 ATL60 TTL109 TTL138 TTL139 TTL148 PDF

    HC 4066A

    Abstract: CMOS 4001, 4011, 4070 and 4081 HC 4053A HC165A HC 4052A HC589A HC00A HC74A 4852A HC 125A
    Text: BUFFERS/INVERTERS ÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ


    Original     		HC4046A HC4538A HC 4066A CMOS 4001, 4011, 4070 and 4081 HC 4053A HC165A HC 4052A HC589A HC00A HC74A 4852A HC 125A PDF

    lm294oct

    Abstract: d71054c D71055C lm294oct-12 74c928 7486 XOR GATE interfacing ADC 0808 with 8086 microprocessor 555 7490 7447 7 segment LED display Motorola 74LS76 NEC D71055C
    Text: Integrated Circuits 74LS Series Featuring better performance than standard 7400 series devices, the 74LS series also uses about 1/5th the power. Part# Pins Description 74LS00 74LS01 74LS02 74LS03 74LS04 74LS05 74LS06 74LS07 74LS08 74LS09 74LS10 74LS11 74LS12


    Original     		74LS00 74LS01 74LS02 74LS03 74LS04 74LS05 74LS06 74LS07 74LS08 74LS09 lm294oct d71054c D71055C lm294oct-12 74c928 7486 XOR GATE interfacing ADC 0808 with 8086 microprocessor 555 7490 7447 7 segment LED display Motorola 74LS76 NEC D71055C PDF

    Untitled

    Abstract: No abstract text available
    Text: Revised November 2004 74VCX132 Low Voltage Quad 2-Input NAND Gate with Schmitt Trigger Inputs and 3.6V Tolerant Inputs and Outputs General Description Features The VCX132 contains four 2-input NAND gates with Schmitt Trigger Inputs. The pin configuration and function


    Original     		74VCX132 VCX132 VCX00 PDF

    TMS 3766

    Abstract: transistors 1UW AN1521 ao21 mx618 MX61H AOI21 H4EP012 H4EP044 H4EP171
    Text: Order this Data Sheet by H4EP/D MOTOROLA bu SEMICONDUCTOR TECHNICAL DATA H4EPlus SERIES Advanced Information H4EPlus SERIES CMOS ARRAYS The H4EPlus Series arrays offer a fully featured 3.3V, 5V and mixed voltage capable family combined with an increased core density providing over 50% more


    Original     		PDF

    atmel 216

    Abstract: ECL IC NAND CQFP 256 PIN actel Atmel 642 PO22 tri state ATL35 atmel 334 20PCI atmel h 952
    Text: Features • High-speed - 150 ps Gate Delay - 2-input NAND, FO = 2 nominal • Up to 2.7 Million Used Gates and 976 Pins • System Level Integration Technology – Cores: ARM7TDMI and AVR RISC Microcontrollers, OakDSP™ and LodeDSPCores™, 10T/100 Ethernet MAC, USB and PCI Cores


    Original     		10T/100 ATL35 0802E 10/99/0M atmel 216 ECL IC NAND CQFP 256 PIN actel Atmel 642 PO22 tri state atmel 334 20PCI atmel h 952 PDF

    74LVT JK Flip Flop

    Abstract: led driver SOT23 6pin lcx244 MOTOROLA lcx 4245 LCX244 quad single supply 50 Ohm Line Drivers diode sj Fairchild Power Switch package to 220 p5 MAX 16841 On semiconductor LCX 574 PA
    Text: 1 Chapter 1 Introduction to Low-Voltage Logic Chapter C R O S S V O L T Parts & Availability 17 Packaging Options 37 Low-Voltage Logic Cross Reference 49 Glossary 57 Fairchild Low-Voltage Logic Reference Guide Chapter Chapter Glossary  Introduction to Low-Voltage Logic


    Original     		PDF

    PTS41

    Abstract: CMOS GATE ARRAY buf8
    Text: ATL60 Features • O.tHim Drawn Gate Length O.Stim Left Sea-of-Gates Architecture With Triple Level Metal • 5.0 Volt, 3.3 Volt, and 2.0 Volt Operation Including Mixed Voltages • On Chip Phase Locked Loop Available to Synthesize Frequencies up to 150 MHz and Manage Chlp-to-Chip Clock Skew


    OCR Scan     		ATL60 ATL60 PTS41 CMOS GATE ARRAY buf8 PDF

    Untitled

    Abstract: No abstract text available
    Text: ATL60 Features • • • • • • • • 0.6|.im D raw n G ate Length 0.5|im Left S e a -o f-G a te s A rch ite c tu re W ith T rip le Level M etal 5.0 V o lt, 3.3 V o lt, and 2.0 V o lt O p e ra tio n In c lu d in g M ixed V o lta g e s On C h ip P h ase Locked Loop A v a ila b le to S y n th e s ize F req u en cies up to


    OCR Scan     		ATL60 ATL60 PDF

    AOI222

    Abstract: P02B OAI222
    Text: ATL50 Features • • • • • • • • 0.5|.im Drawn Gate Length 0.45|am Left Sea-of-Gates Architecture With Triple Level Metal 3.3 Volt Operation 5.0 Volt compatible input buffers On-Chip Phase Locked Loop (PLL) Available to Synthesize Frequencies up to


    OCR Scan     		ATL50 ATL50 AOI222 P02B OAI222 PDF

    T157WG

    Abstract: S-MOS navnet A138G2 t177 4-bit full adder using nand gates and 3*8 decoder 6 input or gate SLA1024 T161RE
    Text: S-M 0 S S Y S T E M S INC 5bE J> m 7 ci3 Z eÏQ'l GG01522 fc.35 H S I 1 0 SLA1 OOOO Series HIGH SPEED CMOS GATE ARRAYS • DESCRIPTION The S-MOS SLA10000 series is a channel-less gate array manufactured on S-MOS’ state-of-the-art 0.8 micron double-metal SiCMOS process. The series consists of 11 arrays ranging from 9,000 to 101,800 usable gates and


    OCR Scan     		GG01522 SLA10000 SSC5000 B8259 B8237 B82284 B8255 T157WG S-MOS navnet A138G2 t177 4-bit full adder using nand gates and 3*8 decoder 6 input or gate SLA1024 T161RE PDF

    8 BIT ALU design with vhdl code using structural

    Abstract: ITE 8515 atmel h 952 vhdl code for watchdog timer of ATM VHDL MAC CHIP CODE real time application of D flip-flop atmel 708 vhdl code for 8 bit barrel shifter 4 BIT ALU design with vhdl code using structural ATL35
    Text: Features * * * * * High Speed - 150 ps Gate Delay - 2 input NAND, FO=2 nominal Up to 3.7 Million Used Gates and 976 Pins System Level Integration Technology CORES: ARM7TDMI and AVA™ RISC Microcontrollers, OakDSP™ and Lode ™DSP Cores, 10T/100 Ethernet MAC, USB and PCI Cores,


    OCR Scan     		10T/100 ATL35 8 BIT ALU design with vhdl code using structural ITE 8515 atmel h 952 vhdl code for watchdog timer of ATM VHDL MAC CHIP CODE real time application of D flip-flop atmel 708 vhdl code for 8 bit barrel shifter 4 BIT ALU design with vhdl code using structural PDF

    real time application of D flip-flop

    Abstract: vhdl code for watchdog timer of ATM atmel 144 0802B
    Text: Features * * * * * High Speed -150 ps Gate Delay 2 input NAND, FO=2 nominal Up to 3.6 Million Used Gates and 1,024 Pins System Level Integration Technology ARM7TDMI and AVfl™ RISC Microcontrollers OakDSP™ and Lode™ DSP Cores 10T/100 Ethernet, USB and PCI Cores


    OCR Scan     		10T/100 ATL35/ATLS35 real time application of D flip-flop vhdl code for watchdog timer of ATM atmel 144 0802B PDF

    6 input or gate

    Abstract: t177 SLA847 986 t04 B8237 B8250 Series A138G2 19275 resistor ssc300 S-MOS asic
    Text: S-H 0 S SYSTEMS INC SbE » • 7ei3StiOti ÜDDlM'ia 076 «SIIO SLA8000 HIGH SPEED CMOS GATE ARRAY ■ DESCRIPTION The SLA8000 Series consists of a group of 13 high speed, sea-of-gates CMOS gate arrays. The series is fabricated utilizing our state-of-the-art 1.2 micron silicon gate technology. Gate counts range from 5K to 80K


    OCR Scan     		SLA8000 SLA8000 SLA827S SLA837S SLA847S SLA860S SLA872S SLA890S SLA86ES 6 input or gate t177 SLA847 986 t04 B8237 B8250 Series A138G2 19275 resistor ssc300 S-MOS asic PDF