ATL60 Search Results

Contextual Info: ATL60 Features • • • • • • • • 0.6|.im D raw n G ate Length 0.5|im Left S e a -o f-G a te s A rch ite c tu re W ith T rip le Level M etal 5.0 V o lt, 3.3 V o lt, and 2.0 V o lt O p e ra tio n In c lu d in g M ixed V o lta g e s On C h ip P h ase Locked Loop A v a ila b le to S y n th e s ize F req u en cies up to

N110

Abstract: N111 P267 ATL60 DLY1500 DLY2000 P109 P123 P162 TI N268
Contextual Info: DLY1500 ATL60 CMOS Gate Array cell data sheets 3.3 DESCRIPTION: Delay buffer 1.5 ns Truth Table: I | O -0 | 0 1 | 1 at60Cells I DLY1500 O VDD! VDD! p P5 p p P30 VDD! p P19 P6 p p P0 VDD! p P18 p P7 p P17 P25<0:1> I O n n N1 n N8 n N16 N24 n N9 VSS!

ATL60

Contextual Info: HLD1 ATL60 CMOS Gate Array cell data sheets 3.3 DESCRIPTION: Bus hold cell Truth Table: X | X -0 | weak0 1 | weak1 at60Cells HLD1 X VDD! p P0 p P10 p P8 VSS! p P33 p P7 p P34 X n N6 n N24 n N25 VDD! n N12 n N26 n N15 VSS! VDD! p P31 n N19 VSS! / $Revision: 1.27 $

n37 transistor

Abstract: n38 transistor P41 transistor P42 transistor ATL60 n38P
Contextual Info: BUF2T ATL60 CMOS Gate Array cell data sheets 3.3 DESCRIPTION: 2x Tri State bus driver with active high enable Truth Table: E I | O -0 X | Z 1 0 | 0 1 1 | 1 at60Cells BUF2T O I E VDD! p P11 VDD! p P4 n N3 p P12 VSS! I O n N5 VDD! N13 VSS! n p VDD! P0

PTS41

Abstract: CMOS GATE ARRAY buf8
Contextual Info: ATL60 Features • O.tHim Drawn Gate Length O.Stim Left Sea-of-Gates Architecture With Triple Level Metal • 5.0 Volt, 3.3 Volt, and 2.0 Volt Operation Including Mixed Voltages • On Chip Phase Locked Loop Available to Synthesize Frequencies up to 150 MHz and Manage Chlp-to-Chip Clock Skew

ATMEL 311

Abstract: atmel 424 credence tester assembly language programs for dft atmel 228 atmel atl ATL60 ATLS60 5003b
Contextual Info: ATL60 Series . Design Manual Table of Contents Section 1 ATL60 Series ASIC. 1-1 1.1 1.2

ATL60

Contextual Info: CLA7X ATL60 CMOS Gate Array cell data sheets 3.3 DESCRIPTION: 7 input carry lookahead Truth Table: at60Cells A A B C D E F G | O -X X X X X X 1 | 0 X X X X 1 1 X | 0 X X 1 1 X 1 X | 0 1 1 X 1 X 1 X | 0 X X X X X 0 0 | 1 X X X 0 0 X 0 | 1

ATL60

Abstract: 4 inputs OR gate
Contextual Info: ATL60SRAMs-3.4-04/98 Memory ATL60 SRAMs Compiled Gate Level Compiled Gate Level SRAMs . 9-2 Common Single Port SRAM Sizes: Table. 9-2

P62d

Abstract: ATL60 1147-000
Contextual Info: LAT ATL60 CMOS Gate Array cell data sheets 3.3 DESCRIPTION: LATCH Truth Table: H D | Q T+1 -0 0 | 0 1 | 1 1 X | Q(T) at60Cells H LAT D Q VDD! VDD! p P58 p P53 p P62 D Q n n N59 N52 N63 n VSS! VSS! VDD! N56 n p P57 p P65 VDD! n VDD!

INCOMING RAW MATERIAL INSPECTION checklist

Abstract: AVR Cores - Complex ASIC Cores - Software ATMEL 311 atmel 424 atmel 545 credence tester ATL60 ATLS60 ATMEL 242 8 pin IC
Contextual Info: ATL60 Series . Design Overview Table of Contents Section 1 ATL60 Series . 1-1

ATL60

Abstract: INV10
Contextual Info: INV1 ATL60 CMOS Gate Array cell data sheets 3.3 DESCRIPTION: 1x inverter Truth Table: INV1 at60Cells1X I I | O -0 | 1 1 | 0 O VDD! p P5 I O n N4 VSS! / $Revision: 1.27 $ Tue Apr 23 12:17:53 1996

max 1786

Abstract: SRAM timing ATL60
Contextual Info: SRAMs-3.3-6/96 Memory ATL60 SRAMs Compiled Gate Level Compiled Gate Level SRAMs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-2 Common Single Port SRAM Sizes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-2

Micron NAND

Abstract: design manual atmel atl ATL25 ATL35
Contextual Info: Below are the ATL25 0.25 micron , ALT35 (0.35 micron) and ATL60/ATLS60 (0.6 micron) design manual sections, followed by five sections which are common to all Atmel design manuals (Design, Test, Packaging, Q&R, and Military & Aerospace). ASIC Checklists Kickoff Meeting Checklist - V 3.2

N117

Abstract: N294 N280 N109 15 N119 CMOS N48 N147 N315 P115 transistor p88
Contextual Info: DFF ATL60 CMOS Gate Array cell data sheets 3.3 DESCRIPTION: D flip-flop Truth Table: CLK D | Q T+1 -RE 0 | 0 RE 1 | 1 FE X | Q(T) at60Cells CLK DFF D Q VDD! VDD! n N73 p n N71 P18 N26 p P34 n VSS! VDD! n N25 p p p n P33 N54 P5 p P13 P8

U386

Abstract: ATL60 U382
Contextual Info: PBSA6T ATL60 CMOS Gate Array cell data sheets 3.3 DESCRIPTION: single enable bi-directional buffer Truth Table: A0 E0 | P AI0 -X | 0 X | 1 1 1 | 0 1 1 | 1 1 at60IO_step80 E0 PBSA6T AO P AI0 VDD! p N45<0:11> AO E0 I370 OP DATA TS IODRVS6 ON

ATL60

Abstract: N109
Contextual Info: NOR2 ATL60 CMOS Gate Array cell data sheets 3.3 DESCRIPTION: 2 input NOR Truth Table: A B | O -0 0 | 1 1 X | 0 X 1 | 0 at60Cells A NOR2 O B VDD! p A P2 p B P0 O n n N10 VSS! / $Revision: 1.27 $

3 to 8 bit decoder vhdl IEEE format

Abstract: ATL60 ATLS60 PO61 ttl buffer
Contextual Info: ATL60 Features x x x x x x x x 0.6Pm Drawn Gate Length 0.5Pm Leff Sea-of-Gates Architecture With Triple Level Metal 5.0 Volt, 3.3 Volt, and 2.0 Volt Operation Including Mixed Voltages On Chip Phase Locked Loop Available to Synthesize Frequencies up to 150 MHz and Manage Chip-to-Chip Clock Skew

ATL60

Abstract: gate drive calculator 0348C
Contextual Info: Gate Array Mixed Voltage Designing ATL60 Series Gate Arrays For Mixed Voltage Operation Introduction As the demand for lower power consumption and voltage has increased the use of 3.3 volt systems, the need for components which can operate in a mixed voltage environment generally,

u386

Abstract: ATL60 N530 234773
Contextual Info: PO4 ATL60 CMOS Gate Array cell data sheets 3.3 DESCRIPTION: output buffer Truth Table: A0 | P -0 | 0 1 | 1 at60IO_step80 PO4 P AO VDD! p N45<0:7> AO I370 DATA OP IODRV4 ON P at60IO I n at60IO N53<0:7> ESD_PROTECT VSS! U381 at60IO IN_LINE_RES_467

TTL Schmitt-Trigger Inverters

Abstract: Structure of D flip-flop DFFSR Tri-State Buffer CMOS TTL 3 input or gate ttl buffer TTL nand 3 input or gate 3 input Decoders actel PLL schematic AOI222
Contextual Info: ATL60 Features • • • • • • • • 0.6µm Drawn Gate Length 0.5µm Leff Sea-of-Gates Architecture With Triple Level Metal 5.0 Volt, 3.3 Volt, and 2.0 Volt Operation Including Mixed Voltages On Chip Phase Locked Loop Available to Synthesize Frequencies up to

Tri-State Buffer CMOS

Abstract: PTS41 books schmitt trigger cmos buffer 8x buffer cmos ATL60 ATLS60 mux8n AOI222
Contextual Info: ATL60 Features • • • • • • • • 0.6µm Drawn Gate Length 0.5µm Leff Sea-of-Gates Architecture With Triple Level Metal 5.0 Volt, 3.3 Volt, and 2.0 Volt Operation Including Mixed Voltages On Chip Phase Locked Loop Available to Synthesize Frequencies up to

RS flip flop cmos

Abstract: 8k x 8 sram design using flip flops vhdl code for watchdog timer of ATM two transistor flip flop cycle count worksheet microcontroller based temperature control fan avr atmel 0748 D flip flop for code vhdl ATL60 ATLS60
Contextual Info: ATL60GA-3.5-04/98 ATL60/ATLS60 Gate Array/Embedded Array Description. 1-2 ATL60 and ATLS60 Array Organizations: Tables . 1-2

ATL60

Abstract: R345
Contextual Info: PKC ATL60 CMOS Gate Array cell data sheets 3.3 DESCRIPTION: clock driver buffer Truth Table: I | O -0 | 0 1 | 1 at60IO_step80 PKC O I VDD! p N45<0:23> I I370 DATA IODRVKC OP ON O at60IO n at60IO N53<0:23> IIN_LINE_RES_467 O R345 VSS! / $Revision: 1.27 $

149-452

Abstract: 101697 PBS3TD31 ATL60 ATLS60 151806 306252 PITU31 07212-1 05666
Contextual Info: ATL60 I/O Buff-3.5-3/98 ATL60/ATLS60 0.6µ I/O Buffer Cell Library I/O Buffer Cell Description . 8-2 ATL60/ATLS60 Series I/O Buffer Naming Conventions . 8-3