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    PIPELINE Search Results

    PIPELINE Result Highlights (5)

    Part ECAD Model Manufacturer Description Download Buy
    29FCT520ALB Renesas Electronics Corporation MULTI-LEVEL PIPELINE REG Visit Renesas Electronics Corporation
    29FCT520ATQ8 Renesas Electronics Corporation MULTI-LEVEL PIPELINE REG Visit Renesas Electronics Corporation
    29FCT520BSO8 Renesas Electronics Corporation MULTI-LEVEL PIPELINE REG Visit Renesas Electronics Corporation
    29FCT520CSO8 Renesas Electronics Corporation MULTI-LEVEL PIPELINE REG Visit Renesas Electronics Corporation
    29FCT520CTSO8 Renesas Electronics Corporation MULTI-LEVEL PIPELINE REG Visit Renesas Electronics Corporation

    PIPELINE Datasheets Context Search

    Catalog Datasheet MFG & Type PDF Document Tags

    Untitled

    Abstract: No abstract text available
    Text: ADS809 ADS 809 www.ti.com 12-Bit, 80MHz Sampling ANALOG-TO-DIGITAL CONVERTER TM FEATURES DESCRIPTION ● DYNAMIC RANGE: SNR: 65dB at 10MHz fIN SFDR: 68dB at 10MHz fIN The ADS809 is a high-dynamic range 12-bit, 80MHz pipelined Analog-to-Digital A/D converter. It includes a


    Original     		PDF ADS809 12-Bit, 80MHz 10MHz ADS809

    Untitled

    Abstract: No abstract text available
    Text: Data sheet acquired from Cypress Semiconductor Corporation. Data sheet modified to remove devices not offered. CY29FCT520T Multi-Level Pipeline Register SCCS011 - May 1994 - Revised February 2000 Features Functional Description • Function, pinout, and drive compatible with FCT, F


    Original     		PDF CY29FCT520T SCCS011 FCT520T

    diode p4e

    Abstract: No abstract text available
    Text: TLC34058 256 x 24 COLOR PALETTE SLAS050 – D3961, NOVEMBER 1991 • • • • • • • • LinEPIC 1-µm CMOS Process 125-MHz Pipelined Architecture Available Clock Rates . . . 80, 110, 125, 135 MHz Dual-Port Color RAM 256 Words x 24 Bits Bit Plane Read and Blink Masks


    Original     		PDF TLC34058 SLAS050 D3961, 125-MHz RS-343-A Bt458 TMS340XX diode p4e

    CQFP352

    Abstract: QFP352 MCGA349 MCGA-349 adc controller vhdl code atmel 268 AT7913 CQFP352 package vhdl code 64 bit FPU SPARC v8 architecture BLOCK DIAGRAM
    Text: ATMEL AT7913E SpaceWire Remote Terminal Controller RTC DATASHEET Features • LEON2-FT Sparc V8 Processor • • • • • • • • • • • 5 stage pipeline 4K instruction caches / 4K data caches Meiko FPU Interrupt Controller Uart serial links


    Original     		PDF AT7913E 32-bit 8bit/16bit 200Mbit/s CQFP352 QFP352 MCGA349 MCGA-349 adc controller vhdl code atmel 268 AT7913 CQFP352 package vhdl code 64 bit FPU SPARC v8 architecture BLOCK DIAGRAM

    Untitled

    Abstract: No abstract text available
    Text: CY7C1368C 9-Mbit 256 K x 32 Pipelined DCD Sync SRAM 9-Mbit (256 K × 32) Pipelined DCD Sync SRAM Functional Description[1] Features • Registered inputs and outputs for pipelined operation ■ Optimal for performance (double-cycle deselect) ❐ Depth expansion without wait state


    Original     		PDF CY7C1368C CY7C1368C

    Untitled

    Abstract: No abstract text available
    Text: CY7C1346H 2-Mbit 64K x 36 Pipelined Sync SRAM Functional Description[1] Features • Registered inputs and outputs for pipelined operation • 64K x 36 common I/O architecture • 3.3V core power supply • 3.3V/2.5V I/O operation • Fast clock-to-output times


    Original     		PDF CY7C1346H 166-MHz 100-pin CY7C1346H 133MHz

    ADS5221

    Abstract: ADS5221PFBR ADS5221PFBT OPA695 QFN-48 THS4503 TQFP-48
    Text: ADS5221 ADS 522 1 SBAS262C – APRIL 2003 – REVISED JUNE 2007 12-Bit, 65MSPS Sampling, +3.3V ANALOG-TO-DIGITAL CONVERTER FEATURES DESCRIPTION ● ● ● ● ● The ADS5221 is a pipeline, CMOS Analog-to-Digital Converter ADC that operates from a single +3.3V power


    Original     		PDF ADS5221 SBAS262C 12-Bit, 65MSPS ADS5221 12-bit ADS5221PFBR ADS5221PFBT OPA695 QFN-48 THS4503 TQFP-48

    MS-026

    Abstract: MT55L256L32P MT55L256L36P MT55L256V32P MT55L256V36P MT55L512L18P MT55L512V18P
    Text: 8Mb: 512K x 18, 256K x 32/36 PIPELINED ZBT SRAM 8Mb ZBT SRAM MT55L512L18P, MT55L512V18P, MT55L256L32P, MT55L256V32P, MT55L256L36P, MT55L256V36P 3.3V VDD, 3.3V or 2.5V I/O FEATURES • • • • • • • • • • • • • • • • • • •


    Original     		PDF MT55L512L18P, MT55L512V18P, MT55L256L32P, MT55L256V32P, MT55L256L36P, MT55L256V36P 100-Pin 119-Pin 165-pin MT55L512L18P MS-026 MT55L256L32P MT55L256L36P MT55L256V32P MT55L256V36P MT55L512V18P

    AS7C331MNTD32A

    Abstract: AS7C331MPFD32A AS7C332MPFD18A AS7C332MPFS18A
    Text: November 2004 AS7C331MNTD32A AS7C331MNTD36A 3.3V 1M x 32/36 Pipelined SRAM with NTDTM Features • Organization: 1,048,576 words × 32 or 36 bits • NTD architecture for efficient bus operation • Fast clock speeds to 200 MHz • Fast clock to data access: 3.2/3.5/3.8 ns


    Original     		PDF AS7C331MNTD32A AS7C331MNTD36A 100-pin 165-ball AS7C331MNTD32A AS7C331MPFD32A AS7C332MPFD18A AS7C332MPFS18A

    A65H73361

    Abstract: A65H83181 SA10 SA11 SA12 SA13 SA15
    Text: A65H73361/A65H83181 Series 128K x 36 & 256K x 18 Late Write Synchronous Fast SRAM with Pipelined Data Output Preliminary Document Title 128K x 36 & 256K x 18 Late Write Synchronous Fast SRAM with Pipelined Data Output Revision History Rev. No. 2.0 PRELIMINARY


    Original     		PDF A65H73361/A65H83181 self65H73361P-7 A65H73361 A65H83181 SA10 SA11 SA12 SA13 SA15

    low input capacitance buffer

    Abstract: A112 A113 WM2331 electrolytic capacitor, .1uF 50v
    Text: WM2331 10-bit 30MSPS ADC with PGA and Clamp DESCRIPTION FEATURES The WM2331 is a high speed, 10-bit pipeline analogue-todigital converter ADC with on-chip programmable gain amplifier (PGA) and clamp circuit, and internal voltage references. Conversion is controlled by a single clock input.


    Original     		PDF WM2331 10-bit 30MSPS WM2331 low input capacitance buffer A112 A113 electrolytic capacitor, .1uF 50v

    K7A323600M

    Abstract: K7B321825M-QC65 K7A321800M
    Text: K7A323600M K7A321800M 1Mx36 & 2Mx18 Synchronous SRAM Document Title 1Mx36 & 2Mx18-Bit Synchronous Pipelined Burst SRAM Revision History Rev. No. History Draft Date Remark 0.0 1. Initial draft May. 10. 2001 Advance 0.1 1. Add 165FBGA package Aug. 29. 2001 Preliminary


    Original     		PDF K7A323600M K7A321800M 1Mx36 2Mx18 2Mx18-Bit 165FBGA K7A3236 165FBGA K7A323600M K7B321825M-QC65 K7A321800M

    MT55L256L18P1T-10A

    Abstract: MS-026 MT55L128L32P1 MT55L128L36P1 MT55L128V32P1 MT55L128V36P1 MT55L256L18P1 MT55L256L18P1T-10 MT55L256V18P1 84 FBGA thermal
    Text: PRELIMINARY 4Mb: 256K x 18, 128K x 32/36 PIPELINED ZBT SRAM 4Mb ZBT SRAM MT55L256L18P1, MT55L256V18P1, MT55L128L32P1, MT55L128V32P1, MT55L128L36P1, MT55L128V36P1 3.3V VDD, 3.3V or 2.5V I/O FEATURES • • • • • • • • • • • • • •


    Original     		PDF MT55L256L18P1, MT55L256V18P1, MT55L128L32P1, MT55L128V32P1, MT55L128L36P1, MT55L128V36P1 August/7/00 119-pin 165-pin MT55L256L18P1 MT55L256L18P1T-10A MS-026 MT55L128L32P1 MT55L128L36P1 MT55L128V32P1 MT55L128V36P1 MT55L256L18P1T-10 MT55L256V18P1 84 FBGA thermal

    A67L7332

    Abstract: A67L7336 A67L8316 A67L8318
    Text: A67L8316/A67L8318/ A67L7332/A67L7336 Series 256K X 16/18, 128K X 32/36 Preliminary LVTTL, Pipelined DBA SRAM Document Title 256K X 16/18, 128K X 32/36 LVTTL, Pipelined DBA SRAM Revision History Rev. No. 0.0 PRELIMINARY History Issue Date Remark Initial issue


    Original     		PDF A67L8316/A67L8318/ A67L7332/A67L7336 100MHz) A67L7332 A67L7336 A67L8316 A67L8318

    IS61DDB21M36

    Abstract: 61DDB22M18 IS61DDB22M18-300M3L IS61DDB22M18 IS61DDB22M18-250M3LI
    Text: 36 Mb 1M x 36 & 2M x 18 DDR-II (Burst of 2) CIO Synchronous SRAMs . I May 2009 Features • 1M x 36 or 2M x 18. • On-chip delay-locked loop (DLL) for wide data valid window. • Common data input/output bus. • Synchronous pipeline read with self-timed late


    Original     		PDF oDDB22M18-250M3L 1Mx36 2Mx18 IS61DDB21M36 61DDB22M18 IS61DDB22M18-300M3L IS61DDB22M18 IS61DDB22M18-250M3LI

    D0-35

    Abstract: IS61QDB42M36 IS61QDB42M36-300M3 IS61QDB44M18 IS61QDB44M18-300M3
    Text: 72 Mb 2M x 36 & 4M x 18 QUAD (Burst of 4) Synchronous SRAMs 7 Q . May 2009 Features • 2M x 36 or 4M x 18. • On-chip delay-locked loop (DLL) for wide data valid window. • Separate read and write ports with concurrent read and write operations. • Synchronous pipeline read with late write operation.


    Original     		PDF IS61QDB42M36-300M3 IS61QDB44M18-300M3 IS61QDB42M36-250M3 IS61QDB44M18-250M3 2Mx36 4Mx18 D0-35 IS61QDB42M36 IS61QDB42M36-300M3 IS61QDB44M18 IS61QDB44M18-300M3

    IS61QDB41M36

    Abstract: 61QDB41M36 IS61QDB41M36-250M3L D0-35 IS61QDB41M36-250M3 IS61QDB42M18
    Text: 36 Mb 1M x 36 & 2M x 18 QUAD (Burst of 4) Synchronous SRAMs . I April 2009 Features • 1M x 36 or 2M x 18. • On-chip delay-locked loop (DLL) for wide data valid window. • Separate read and write ports with concurrent read and write operations. • Synchronous pipeline read with late write operation.


    Original     		PDF IS61QDB41M36-250M3 IS61QDB41M36-250M3L IS61QDB41M36-200M3 IS61QDB42M18-200M3 1Mx36 2Mx18 IS61QDB41M36 61QDB41M36 IS61QDB41M36-250M3L D0-35 IS61QDB41M36-250M3 IS61QDB42M18

    K7A401800B-QC

    Abstract: K7A401809B K7A401809B-QC K7A403200B-QC K7A403209B K7A403209B-QC K7A403609B K7B401825B-QC K7B403225B-QC
    Text: K7A403609B K7A403209B K7A401809B 128Kx36/x32 & 256Kx18 Synchronous SRAM Document Title 128Kx36 & 128Kx32 & 256Kx18-Bit Synchronous Pipelined Burst SRAM Revision History History Draft Date Remark 0.0 1. Initial draft May. 15. 2001 Preliminary 0.1 1. Changed DC parameters


    Original     		PDF K7A403609B K7A403209B K7A401809B 128Kx36/x32 256Kx18 128Kx36 128Kx32 256Kx18-Bit 570mA 490mA K7A401800B-QC K7A401809B K7A401809B-QC K7A403200B-QC K7A403209B K7A403209B-QC K7A403609B K7B401825B-QC K7B403225B-QC

    CY7C1339

    Abstract: No abstract text available
    Text: fax id: 1109 PRELIMINARY CY7C1339 128K x 32 Synchronous-Pipelined Cache RAM Features Functional Description • Low 1.65 mW standby power (f=0, L version) The CY7C1339 is a 3.3V 128K by 32 synchronous-pipelined cache SRAM designed to support zero wait state secondary


    Original     		PDF CY7C1339 CY7C1339 100-MHz 166-MHz

    MoSys

    Abstract: CL018G tsmc 0.18um MoSys sram embedded BWEB M1T1HT18PZ32E C-l018 32K32 MoSys 1T sram
    Text: High Speed Pipelined 1-Mbit 32Kx32 Standard 1T-SRAM Embedded Memory Macro M1T1HT18PZ32E • High Performance 1T-SRAM Standard Macro • 200 MHz operation • 1-Clock cycle time • Pipelined read access timing • Late-late write mode timing • 32-Bit wide data buses


    Original     		PDF 32Kx32) M1T1HT18PZ32E 32-Bit CL018G 2300um 32Kx32 1650um M1T1HT18PZ32E MoSys tsmc 0.18um MoSys sram embedded BWEB C-l018 32K32 MoSys 1T sram

    GS8161Z18AT-300

    Abstract: gs816
    Text: Preliminary GS8161Z18/36AT-300/275/250/225/200 18Mb Pipelined and Flow Through Synchronous NBT SRAM Flow Through 2-1-1-1 1.8 V 2.5 V 300 345 300 340 275 320 275 315 250 295 250 285 230 265 225 260 mA mA mA mA tKQ tCycle 5.0 5.0 5.25 5.25 5.5 5.5 6.0 6.0 6.5


    Original     		PDF GS8161Z18/36AT-300/275/250/225/200 GS8161Z18/36AT 100-pin 8161Z18A GS8161Z18AT-300 gs816

    Untitled

    Abstract: No abstract text available
    Text: TOSHIBA TC55V2325FF-100 TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS 65,536 W O R D x 32 BIT Synchronous Pipelined Burst SRAM DESCRIPTION The TC55V2325FF is a 2 ,0 9 7 ,1 5 2 bit synchronous pipelined burst SRAM that is organized as 65,536 words by 32 bits and designed for use in a secondary cache to support MPUs which have burst


    OCR Scan     		PDF TC55V2325FF-100 TC55V2325FF 64KX32 LQFP100-P-1420-0

    UM61L3232AF-7

    Abstract: UM61L3232A um61 UM61L UM61L3232 UM61L3232AF-8 UM61-l-3232af
    Text: UM61L3232A Series PRELIMINARY 32K X 32 Bit Synchronous High Speed SRAM with Burst Counter and Pipelined Data Output Features Fast access times: 5/6/7/8 ns Single +3.3V+10% or +3.3V-5% power supply Synchronous burst function Individual Byte W rite control and Global Write


    OCR Scan     		PDF UM61L3232A 100-pin 10jiA. UM61L3232AF-5 UM61L3232AE-5 UM61L3232AF-6 UM61L3232AE-6 UM61L3232AF-7 UM61L3232AE-7 um61 UM61L UM61L3232 UM61L3232AF-8 UM61-l-3232af

    AxC11

    Abstract: No abstract text available
    Text: N EC ELECTRONICS INC dEEC ^ t 7 E 1 • tMS7S2S DG3R58b MM3 H N E C E _ 16Mbit Synchronous DRAM_ CONTENTS Programable 3 - stage pipeline. Features.


    OCR Scan     		PDF DG3R58b 16Mbit bM27S25 AxC11