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Catalog Datasheet	Type	Document Tags	PDF
Untitled Abstract: No abstract text available Text: ATL60 Features • • • • • • • • 0.6\|.im D raw n G ate Length 0.5\|im Left S e a -o f-G a te s A rch ite c tu re W ith T rip le Level M etal 5.0 V o lt, 3.3 V o lt, and 2.0 V o lt O p e ra tio n In c lu d in g M ixed V o lta g e s On C h ip P h ase Locked Loop A v a ila b le to S y n th e s ize F req u en cies up to	OCR Scan	ATL60 ATL60	PDF
PTS41 Abstract: CMOS GATE ARRAY buf8 Text: ATL60 Features • O.tHim Drawn Gate Length O.Stim Left Sea-of-Gates Architecture With Triple Level Metal • 5.0 Volt, 3.3 Volt, and 2.0 Volt Operation Including Mixed Voltages • On Chip Phase Locked Loop Available to Synthesize Frequencies up to 150 MHz and Manage Chlp-to-Chip Clock Skew	OCR Scan	ATL60 ATL60 PTS41 CMOS GATE ARRAY buf8	PDF
U386 Abstract: ATL60 U382 Text: PBSA6T ATL60 CMOS Gate Array cell data sheets 3.3 DESCRIPTION: single enable bi-directional buffer Truth Table: A0 E0 \| P AI0 -X \| 0 X \| 1 1 1 \| 0 1 1 \| 1 1 at60IO_step80 E0 PBSA6T AO P AI0 VDD! p N45<0:11> AO E0 I370 OP DATA TS IODRVS6 ON	Original	ATL60 at60IO step80 at60IO 25degC U386 U382	PDF
3 to 8 bit decoder vhdl IEEE format Abstract: ATL60 ATLS60 PO61 ttl buffer Text: ATL60 Features x x x x x x x x 0.6Pm Drawn Gate Length 0.5Pm Leff Sea-of-Gates Architecture With Triple Level Metal 5.0 Volt, 3.3 Volt, and 2.0 Volt Operation Including Mixed Voltages On Chip Phase Locked Loop Available to Synthesize Frequencies up to 150 MHz and Manage Chip-to-Chip Clock Skew	Original	ATL60 ATL60 3 to 8 bit decoder vhdl IEEE format ATLS60 PO61 ttl buffer	PDF
TTL Schmitt-Trigger Inverters Abstract: Structure of D flip-flop DFFSR Tri-State Buffer CMOS TTL 3 input or gate ttl buffer TTL nand 3 input or gate 3 input Decoders actel PLL schematic AOI222 Text: ATL60 Features • • • • • • • • 0.6µm Drawn Gate Length 0.5µm Leff Sea-of-Gates Architecture With Triple Level Metal 5.0 Volt, 3.3 Volt, and 2.0 Volt Operation Including Mixed Voltages On Chip Phase Locked Loop Available to Synthesize Frequencies up to	Original	ATL60 ATL60 TTL Schmitt-Trigger Inverters Structure of D flip-flop DFFSR Tri-State Buffer CMOS TTL 3 input or gate ttl buffer TTL nand 3 input or gate 3 input Decoders actel PLL schematic AOI222	PDF
Tri-State Buffer CMOS Abstract: PTS41 books schmitt trigger cmos buffer 8x buffer cmos ATL60 ATLS60 mux8n AOI222 Text: ATL60 Features • • • • • • • • 0.6µm Drawn Gate Length 0.5µm Leff Sea-of-Gates Architecture With Triple Level Metal 5.0 Volt, 3.3 Volt, and 2.0 Volt Operation Including Mixed Voltages On Chip Phase Locked Loop Available to Synthesize Frequencies up to	Original	ATL60 ATL60 Tri-State Buffer CMOS PTS41 books schmitt trigger cmos buffer 8x buffer cmos ATLS60 mux8n AOI222	PDF
149-452 Abstract: 101697 PBS3TD31 ATL60 ATLS60 151806 306252 PITU31 07212-1 05666 Text: ATL60 I/O Buff-3.5-3/98 ATL60/ATLS60 0.6µ I/O Buffer Cell Library I/O Buffer Cell Description . 8-2 ATL60/ATLS60 Series I/O Buffer Naming Conventions . 8-3	Original	ATL60 ATL60/ATLS60 149-452 101697 PBS3TD31 ATLS60 151806 306252 PITU31 07212-1 05666	PDF
PO61 Abstract: ATMEL 340 atmel 424 ATLS60 ATL60 ttl buffer 3.6v Tri-State Buffer bga ambit inverter circuit AOI222 ATMEL 218 Text: Features • • • • • • • • 0.6 µm Drawn Gate Length 0.5 µm Leff Sea-of-Gates Architecture with Triple Level Metal 5.0V, 3.3V and 2.0V Operation including Mixed Voltages On-chip Phase Locked Loop Available to Synthesize Frequencies up to 150 MHz and	Original	ATL60 0388C 11/99/xM PO61 ATMEL 340 atmel 424 ATLS60 ttl buffer 3.6v Tri-State Buffer bga ambit inverter circuit AOI222 ATMEL 218	PDF
74ALS283 Abstract: 74ALS148 74ALS194 0-99 counter by using 4 dual jk flip flop 004887 ATL60 TTL109 TTL138 TTL139 TTL148 Text: Cell Library Index How to Use This Cell Library Index The cell index contains the macro cell’s timing, size and loading information. The data included in the cell timing information is explained in detail below. Cell Parameters Sites: Lists the number of gate array cell sites the macrocell occupies. This can be	Original	ATL50 ATL60 DP32x36) 74ALS283 74ALS148 74ALS194 0-99 counter by using 4 dual jk flip flop 004887 ATL60 TTL109 TTL138 TTL139 TTL148	PDF
A/ATMEL 0843 Abstract: No abstract text available Text: ATL80 - 0.8 µ I/O Buffer Cells Typical Delays at Tj = 25°C; Vdd = 5.0 V; Input Rise and Fall Times = 1 ns; Process = Nominal Sample of buffers composed of modular I/O building blocks Cell Name Description (Site Count) PBD2C 4 mA bidi CMOS buffer (1) PBD3C	Original	ATL80 PBD32TS A/ATMEL 0843	PDF