L12XL6B Search Results

16X24

Contextual Info: QL16x24B/QL16x24BH WildCat 4000 Very-High-Speed 4K 12K Gate CMOS FPGA Rev B pASIC HIGHLIGHTS B Very High Speed - V iaL ink metal-to-metal program m able-via anti­ fuse technology, allows counter speeds over 150 MHz and logic cell delays of under 2 ns.

QL12x16B

Abstract: ic 236
Contextual Info: Q L12x16B WildCat 2000 Very-High-Speed 2K 6K Gate CMOS FPGA pASIC HIGHLIGHTS .6000 total available gates, 88 input pins Q Very High Speed - ViaLink metal-to-metal programmable-via anti-fuse technology, allows counter speeds over 150 MHz and logic cell delays of

Contextual Info: QL12x16B W ildCat 2000 Very-High-Speed 2K 6K Gate CMOS FPGA pASIC HIGHLIGHTS Very High Speed - ViaLink metal-to-metal programmable-via anti-fuse technology, allows counter speeds over 150 MHz and logic cell delays of under 2 ns. B High Usable Density - A 12-by-16 array of 192 logic cells provides 6000

pl84c

Contextual Info: QL12x16BL pASIC 1 Family Low Power 3.3 Volt Operation FPGA pASIC HIGHLIGHTS High Speed - ViaLink metal-to-metal program m able-via antifuse technology, allows counter speeds over 80 MHz at 3.3 Volt operation. 5V Tolerant I/Os - Support interface to 5 Volt CMOS, NMOS and

pl68c

Contextual Info: QL8X12B pASIC 1 Family Very-High-Speed CMOS FPGA Rev B pASIC HIGHLIGHTS S Very High Speed - ViaLink metal-to-metal program m able-via antifuse technology, allows counter speeds over 150 MHz and logic cell delays o f under 2 ns. .1,000 E High Usable Density - An 8-by-12 array of 96 logic cells provides

Contextual Info: Q L16X24B pASIC 1 Family Very-High-Speed CMOS FPGA Rev C pASIC HIGHLIGHTS .4,000 usable ASIC gates, 122 I/O pins Very High Speed - ViaLink metal-to-metal program m able-via antifuse technology, allows counter speeds over 150 MHz and logic cell delays of under 2 ns.