IRD12 Search Results

Contextual Info: 54SXFamily FPGAs Leadi ng Edge P e r f o r m a nc e • • 320 MHz Internal Performance • 3.3VOperation with 5.0YInput Tolerance • 3.7 ns Qock-to-Out Pin-to-Pin • • 0.1ns Input Set-Up • Deterministic, Ufcer-Controllable Timing • 0.25 ns d o c k Skew

ACTEL BGA329

Abstract: LRD12 54SX A54SX08 A54SX16 A54SX32 PAR64 REQ64 LRD-12 A54SX16P PQFP
Contextual Info: -m e te f v 3 .0 - m 54SX Fami ly FPGAs Leadi ng Edge P e r f o r m a n c e • • 320 MHz Internal Performance • 3.3VOperation with 5.0YInput Tolerance • 3.7 ns Qock-toOut Pin-to-Pin • \fcry Low Power Consumption

Contextual Info: P r e l i m i n a r y v 1 .3 54SXFamily FPGAs RadTolerant and HiRcl Features • 100%Resource Utilization with 100%Pin Locking R a d T o l e r a n t 5 4 S X F am i l y • Mxed Voltage Support— 3.3VOperation with 5.0VInput Tolerance • Tested Total IonizingDose TID Survivability Level

Contextual Info: 54SX Family FPGAs RadTolerant and HiRel Features R a d T ole ran t 54SX Family • • • • • TestedTotal Ionizing Dose TID Survivability Level Devices Avail able from Tested Lots Radiation Performance to 100K Rads Up to 160 MHz On-Chip Performance

b23n20

Contextual Info: ^ c te -m v 2. 0 l 54SX Family FPGAs • • • • • 100%Resource Utilization with 100%Pin Locking 3.3VOperation with 5.0VInput Tolerance Very Low Power Consumption Deterministic, User-ControlIableTiming Unique, In-System Diagnostic and Debug capability with

THERMAL Fuse m20 tf 115 c

Abstract: 54SX16A actel fpga 54sx32 54SX32
Contextual Info: ^ c te l v 2 .0 54SX Family FPGAs L ea d in g Edge Pe rform an ce • 100% Resource Utilization with 100%Pin Locking • 320 MHz Internal Performance • 3.3V Operation with 5.0V Input Tolerance • 3.7 ns Clock-to-Out Pm-to-Pin • Very Low Power Consumption

Contextual Info: W ie te l Preüminary - m v1 . 2 54SXFamily FPGAs RadTolerant and HiRcl Features • 100%Resource Utilization with 100%Pin Locking R a d T o l e r a n t 5 4 S X F am i l y • Mxed Voltage Support— 3.3VOperation with 5.0VInput

ird8

Abstract: LRD12 54SX32 ic tny 176 TNY 227 TNY 251
Contextual Info: ^ c te l P re lim in a ry v l.1 54SX Family FPGAs RadTolerant and HiRel F e a tu re s R a d T o le r a n t 5 4 S X F a m ily • • • • • Tested Total Ionizing Dose TID Survivability Level Devices Available from Tested Lots Radiation Performance to 100K Rads

IRD4553

Contextual Info: INSTR D ES IG N/ DISPLA Y PDTS Q P IA GS D | LÂBÜ0IP LOTI tiL I T D @ I N l EMITTED COLOR LENS TYPE & COLOR PREFIX T m \m m i 1R£ HD IfM IMF IHC .IS m RED DIFFUSED WHITE DIFFUSED RED TRANSPARENT WATER CLEAR RED DIFFUSED WHITE DIFFUSED RED TRANSPARENT

transistor P7o

Abstract: H30P 54SX16
Contextual Info: Preliminary v 1 .0 54SX Family FPGAs Features • Unique, In-System Diagnostic and Debug Facility with Silicon Explorer High Perform ance • JTAG Boundary Scan Testing In Compliance with IEEE • 320 MHz I nternal Performance • 4.0 ns Cl ock-to-Out Pin-to-Pin

LRD12

Abstract: IRD12
Contextual Info: 54SX Family FPGAs Features • 3.3VOperation with 5.0VInput Tolerance High • Low Power Consumption Perform ance • 320 MHz I nternal Performance • Deterministic, User-ControlIableTiming • 4.0 ns Cl ock-to-Out Pin-to-Pin • Unique, In-System Diagnostic and Debug Facility with

A54SX08A

Abstract: FBGA-484 LRD12 A54SX16 A54SX16A A54SX32A A54SX72A PAR64 REQ64 54SX72
Contextual Info: Æ ic te ! P r e l i m i n a r y v1 .1 - m SX-AFamily FPGAs L e a d i n g E d g e Pe r f o r m a n e e • Configurable I/O Support for 3.3V5.0VPC3, LVTTL, and TIL • 250 MHz System Performance • Configurable Wfcak Resistor Pullup or Pulldown for