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    CQ208 Search Results

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    CQ208 Price and Stock

    Rochester Electronics LLC EP20K200CQ208C7

    LOADABLE PLD, 1.48NS PQFP208
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    DigiKey EP20K200CQ208C7 Bulk 284 2
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    Rochester Electronics LLC EP20K200CQ208C8

    LOADABLE PLD, 1.78NS PQFP208
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    DigiKey EP20K200CQ208C8 Bulk 83 3
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    BPM Microsystems Inc LSOCQ208EA

    LSOCQ208EA Socket Card for BPM P
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    DigiKey LSOCQ208EA 1
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    Microchip Technology Inc AX250-1CQ208M

    IC FPGA 115 I/O 208CQFP
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    EBV Elektronik AX250-1CQ208M 45 Weeks 2
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    Microchip Technology Inc APA600-CQ208B

    IC FPGA 158 I/O 208CQFP
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    DigiKey APA600-CQ208B Bulk 1
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    Mouser Electronics APA600-CQ208B
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    Newark APA600-CQ208B Bulk 1
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    Microchip Technology Inc APA600-CQ208B 41 28 Weeks
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    NAC APA600-CQ208B Box 1
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    Avnet Silica APA600-CQ208B 38 Weeks 1
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    EBV Elektronik APA600-CQ208B 41 Weeks 1
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    Master Electronics APA600-CQ208B
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    CQ208 Datasheets Context Search

    Catalog Datasheet Type Document Tags PDF

    UT6325

    Abstract: 484-CLGA CL484 CQFP 208 datasheet PBGA 484P UT-SG-CQ208 CQ208 QT-SG-PS484
    Text: RadHard Eclipse Devices UT6325-W* 208-PQFP 9 N/A UT8RHEEB-208PC UT8RHE-SKT208P N/A N/A QT-SG-PQ208 9 UT6325-X* 208-CQFP 9 9 UT8RHEEB-208PC UT8RHE-SKT208C UT8RHE-SKT208P with proper land pads 9 UT-SG-CQ208 9 UT6325-P* 280-PBGA 9 N/A UT8RHEEB-288PC UT8RHE-SKT280P


    Original     		UT6325-W* 208-PQFP UT8RHEEB-208PC UT8RHE-SKT208P UT8RHE-SKT208C UT8RHEEB-288PC UT8RHE-SKT280P UT6325 484-CLGA CL484 CQFP 208 datasheet PBGA 484P UT-SG-CQ208 CQ208 QT-SG-PS484 PDF

    antifuse programming technology

    Abstract: 40MX 42MX A40MX02 A40MX04 A42MX09 A42MX16 A42MX24 A42MX36 42MX24
    Text: v6.0 40MX and 42MX FPGA Families Fe a t ur es High C apaci t y • • • • • • Commercial, Military Temperature, and MIL-STD-883 Ceramic Packages Single-Chip ASIC Alternative 3,000 to 54,000 System Gates Up to 2.5 kbits Configurable Dual-Port SRAM


    Original     		MIL-STD-883 35-Bit antifuse programming technology 40MX 42MX A40MX02 A40MX04 A42MX09 A42MX16 A42MX24 A42MX36 42MX24 PDF

    Actel A1225

    Abstract: PL84 A1240XL actel a1240 A32140 PQ100C Cadence TQ176 PG176
    Text: ^ c te l - w Integrator Series FPGAs: 1200XL and 3200DX Famüies Features a 4 L. ¡§ Cadence, Escalade, Exemplar, 1ST, Mentor Graphics, Synopsvs, and Viewlogic. High C a p a c ity • IEEE Standard 1149.1 JTAG Boundary Scan Testing.


    OCR Scan     		1200XL 3200DX A1225 A1240 A3265 A1280 A32100 A32140 Actel A1225 PL84 A1240XL actel a1240 PQ100C Cadence TQ176 PG176 PDF

    Untitled

    Abstract: No abstract text available
    Text: Æ ic te - m ! v 2 .0 Radiation-Hardened Field Programmable Gate Arrays Features Guaranteed Total Dose Radiation Capability Low Single Event Upset Susceptibility High Dose Rate Survivability Latch-Up Im m unity Guaranteed QML Qualified Devices


    OCR Scan     		RH1020 RH1280 CCS08and CQ256, PDF

    RA 8040

    Abstract: transistor SMD c5c phl 409 64x4 memory SMD cq 603 transistor BIM G18 Y1 smd transistor asy CQ256
    Text: m e te ! v3 .0 - m 40MX and 42MX Families FPGAs F e a tu re s • QML Certification H ig h C a p a c ity • Ceramic Devices Available to DSCC SMD • Single Chip ASIC Alternative E a s e o f In t e g r a tio n • 2,000 to 36,000 Available Logic Gates


    OCR Scan     		PBGA272 RA 8040 transistor SMD c5c phl 409 64x4 memory SMD cq 603 transistor BIM G18 Y1 smd transistor asy CQ256 PDF

    GHL 8

    Abstract: FPGA 144 CPGA 172 PLCC ASIC actel a1240 a1280xlf
    Text: Integrator SeriesFPGAs: 1200XL and 3200DX Families Features Cadence, Escalade, E xem plar, 1ST, M e n to r G raphics, Synopsys, and V iew logic. High C a p a c i t y • • 2,500 to 40,000 Logic Gates • Up to 4 K b its C o n fig u ra b le D ual-Port SRAM


    OCR Scan     		1200XL 3200DX 1200XL 3200DX GHL 8 FPGA 144 CPGA 172 PLCC ASIC actel a1240 a1280xlf PDF

    LGA 478 SOCKET PIN LAYOUT

    Abstract: RTAX2000
    Text: v5.2 RTAX-S/SL RadTolerant FPGAs Radiation Performance Leading-Edge Performance • • • • • • • • • • SEU-Hardened Registers Eliminate the Need for TripleModule Redundancy TMR – Immune to Single-Event Upsets (SEU) to LETTH > 37 MeV-cm2/mg


    Original     		TM1019 LGA 478 SOCKET PIN LAYOUT RTAX2000 PDF

    rt54sx32su

    Abstract: RTSX72 RTSX32SU RTSX72-S
    Text: Advanced v0.1 RTSX-SU RadTolerant FPGAs UMC u e Designed for Space • • • • • SEU-Hardened Registers Eliminate the Need to Implement Triple-Module Redundancy (TMR) – Immune to Single-Event Upsets (SEU) to LETth > 40 MeV-cm2/mg, – SEU Rate < 10–10 Upset/Bit-Day in Worst-Case


    Original     		TM1019 rt54sx32su RTSX72 RTSX32SU RTSX72-S PDF

    Untitled

    Abstract: No abstract text available
    Text: v5.0 ProASICPLUS TM Flash Family FPGAs Features and Benefits • High Capacity High Performance Routing Hierarchy Commercial and Industrial • • • • • • • 75,000 to 1 Million System Gates 27 k to 198 kbits of Two-Port SRAM 66 to 712 User I/Os


    Original     		PDF

    RAM256X9SST

    Abstract: ProASICPLUS Flash Family FPGAs v5.0
    Text: v5.0 ProASICPLUS TM Flash Family FPGAs Features and Benefits • High Capacity High Performance Routing Hierarchy Commercial and Industrial • • • • • • • 75,000 to 1 Million System Gates 27 k to 198 kbits of Two-Port SRAM 66 to 712 User I/Os


    Original     		APA075, APA150, APA300 RAM256X9SST ProASICPLUS Flash Family FPGAs v5.0 PDF

    Untitled

    Abstract: No abstract text available
    Text: v2 . 1 RTSX-S RadTolerant FPGAs Designed for Space • • • • • SEU-Hardened Registers Eliminate the Need to Implement Triple-Module Redundancy TMR – Immune to Single-Event Upsets (SEU) to LETth > 40 MeV-cm2/mg, – SEU Rate < 10–10 Upset/Bit-Day in Worst-Case


    Original     		TM1019 PDF

    RTAX2000

    Abstract: schematic diagram 2 sc 1020 RTAX1000 RTAX250 Synplify tmr RTAX2000S
    Text: A dv an c ed v0 .5 RTAX-S RadTolerant FPGAs Designed for Space • • • • • • • • SEU-Hardened Registers Eliminate the Need for Triple-Module Redundancy TMR – Immune to Single-Event Upsets (SEU) to LETth > 60 MeV-cm2/mg – SEU Rate < 10-10 Errors/Bit-Day in Worst-Case


    Original     		TM1019 com/documents/CQ352FPGA RTAX2000 schematic diagram 2 sc 1020 RTAX1000 RTAX250 Synplify tmr RTAX2000S PDF

    CQFP 256 PIN actel

    Abstract: No abstract text available
    Text: Pr el i mi nar y v 1. 3 54SX Family FPGAs RadTolerant and HiRel Features • 100% Resource Utilization with 100% Pin Locking RadTolerant 54SX Family • Mixed Voltage Support—3.3V Operation with 5.0V Input Tolerance • Tested Total Ionizing Dose TID Survivability Level


    Original     		PDF

    RTAX2000

    Abstract: footprint cqfp 280 RTAX1000S actel cqfp 84
    Text: A dv an c ed v0 .5 RTAX-S RadTolerant FPGAs Designed for Space • • • • • • • • SEU-Hardened Registers Eliminate the Need for Triple-Module Redundancy TMR – Immune to Single-Event Upsets (SEU) to LETth > 60 MeV-cm2/mg – SEU Rate < 10-10 Errors/Bit-Day in Worst-Case


    Original     		TM1019 RTAX2000 footprint cqfp 280 RTAX1000S actel cqfp 84 PDF

    APA075

    Abstract: No abstract text available
    Text: v4.1 ProASICPLUS TM Flash Family FPGAs Features and Benefits High Capacity Commercial and Industrial • • • 75,000 to 1 Million System Gates 27 k to 198 kbits of Two-Port SRAM 66 to 712 User I/Os Military and Mil-Std 883B • • • 300, 000 to 1 million System Gates


    Original     		APA075, APA150, APA300 APA075 PDF

    M2GL005

    Abstract: A2F060
    Text: Power Matters. CO LUT4 C OVFL LO UB ADD_S FPGA and SoC Product +/- Catalog ] A[17:0 D EN RO IN YP EN _SR CLK RST EN X ] C[43:0 SL D SN[43 D ] B[17:0 17 SHIFT >> 17 ASC SEL_C SECURITY RELIABILITY LOW POWER :0] SN-1[43 I N T E G R AT I O N FPGAs SoC FPGAs


    Original     		MS2-002-14 M2GL005 A2F060 PDF

    0116 solar 4 pins

    Abstract: 8ag marking equivalent transistor A1020 y 7 b RH1280
    Text: v 2. 0 Radiation-Hardened Field Programmable Gate Arrays Features • Guaranteed Total Dose Radiation Capability • Low Single Event Upset Susceptibility • High Dose Rate Survivability • Latch-Up Immunity Guaranteed • QML Qualified Devices • Commercial Devices Available for Prototyping and


    Original     		20-Pin RH1020 RH1280 CQ208 CQ256, 0116 solar 4 pins 8ag marking equivalent transistor A1020 y 7 b PDF

    56 pin edac connector

    Abstract: PCB footprint cqfp 132 Silicon Sculptor II ACTEL CCGA 624 mechanical
    Text: v2.0 RTAX-S RadTolerant FPGAs Designed for Space • • • • • • • • SEU-Hardened Registers Eliminate the Need for Triple-Module Redundancy TMR – Immune to Single-Event Upsets (SEU) to LETTH > 37 MeV-cm2/mg – SEU Rate < 10-10 Errors/Bit-Day in Worst-Case


    Original     		TM1019 56 pin edac connector PCB footprint cqfp 132 Silicon Sculptor II ACTEL CCGA 624 mechanical PDF

    1kx8 static ram

    Abstract: No abstract text available
    Text: v5.1 ProASICPLUS ® Flash Family FPGAs Features and Benefits High Performance Routing Hierarchy • • • • High Capacity Commercial and Industrial • • • I/O 75,000 to 1 Million System Gates 27 k to 198 kbits of Two-Port SRAM 66 to 712 User I/Os


    Original     		32-Bit APA075, APA150, APA300 1kx8 static ram PDF

    RTSX32su

    Abstract: Actel a54sx72a tid Silicon Sculptor II
    Text: v2.2 RTSX-SU RadTolerant FPGAs UMC u e Designed for Space • • • • • SEU-Hardened Registers Eliminate the Need to Implement Triple-Module Redundancy (TMR) – Immune to Single-Event Upsets (SEU) to LETth > 40 MeV-cm2/mg, – SEU Rate < 10–10 Upset/Bit-Day in Worst-Case


    Original     		TM1019 RTSX32su Actel a54sx72a tid Silicon Sculptor II PDF

    HiRel a54sx72a unused

    Abstract: No abstract text available
    Text: Advanced v1.6 RTSX-S RadTolerant FPGAs for Space Application S p ec i a l F e a tu r es fo r S p ac e • First Actel FPGA Designed Specifically for Space Applications • Up to 2,012 SEU Hardened Flip-Flops Eliminate Software TMR Necessity LET th > 40, GEO SEU Rate < 10–10


    Original     		TM1019 HiRel a54sx72a unused PDF

    RTAX2000

    Abstract: rtax4000 CDB 455 C34 IO358 DIODE SMD V05 128X3
    Text: v5.1 RTAX-S/SL RadTolerant FPGAs Radiation Performance Leading-Edge Performance • • • • • • • • • • SEU-Hardened Registers Eliminate the Need for TripleModule Redundancy TMR – Immune to Single-Event Upsets (SEU) to LETTH > 37 MeV-cm2/mg


    Original     		TM1019 RTAX2000 rtax4000 CDB 455 C34 IO358 DIODE SMD V05 128X3 PDF

    OB25LPLL

    Abstract: diagram LG 21 fs 4 bg model circuits MIL-STD-8831 RAM256X9AA APA075
    Text: v5.5 ProASICPLUS ® Flash Family FPGAs Features and Benefits High Performance Routing Hierarchy • • • • High Capacity Commercial and Industrial • • • I/O 75,000 to 1 Million System Gates 27 k to 198 kbits of Two-Port SRAM 66 to 712 User I/Os


    Original     		32-Bit APA075, APA150, APA300 OB25LPLL diagram LG 21 fs 4 bg model circuits MIL-STD-8831 RAM256X9AA APA075 PDF

    RTSX32su

    Abstract: RTSX32SU CQ84 RTSX72SU
    Text: v2.0 RTSX-SU RadTolerant FPGAs UMC u e Designed for Space • • • • • SEU-Hardened Registers Eliminate the Need to Implement Triple-Module Redundancy (TMR) – Immune to Single-Event Upsets (SEU) to LETth > 40 MeV-cm2/mg, – SEU Rate < 10–10 Upset/Bit-Day in Worst-Case


    Original     		TM1019 RTSX32su RTSX32SU CQ84 RTSX72SU PDF