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    EP9101 Search Results

    EP9101 Datasheets (1)

    Part ECAD Model Manufacturer Description Curated Datasheet Type PDF
    EP9101 PCA Electronics SMD 28 Pin 5 Tap TTL Compatible Active Delay Line Original PDF

    EP9101 Datasheets Context Search

    Catalog Datasheet MFG & Type Document Tags PDF

    EP9100

    Abstract: EP9122 EP9108 EP9109 EP9110 EP9111 EP9112 EP9113 EP9114 EP9129
    Text: 28 Pin SMD 5 Tap TTL Compatible Active Delay Lines ELECTRONICS INC. EP9100 to EP9129 & EP9100-RC to EP9129-RC Add “-RC” after part number for RoHS Compliant J-Lead Part Number EP9100 -RC EP9101(-RC) EP9102(-RC) EP9103(-RC) EP9104(-RC) EP9105(-RC) EP9106(-RC)


    Original     		EP9100 EP9129 EP9100-RC EP9129-RC EP9101 EP9102 EP9103 EP9104 EP9105 EP9122 EP9108 EP9109 EP9110 EP9111 EP9112 EP9113 EP9114 EP9129 PDF

    Untitled

    Abstract: No abstract text available
    Text: SMD 28 Pin 5 Tap TTL Compatible Active Delay Lines Delays are ±5% or ±2 nS† Tap Total 5, 10, 15, 20 6, 12, 18, 24 7, 14, 21, 28 8, 16, 24, 32 9, 18, 27, 36 10, 20, 30, 40 12, 24, 36, 48 15, 30, 45, 60 J-Lead P/N 25 30 35 40 45 50 60 75 †Whichever is greater.


    Original     		EP9100 EP9101 EP9102 EP9103 EP9104 EP9105 EP9106 EP9107 EP9115 EP9116 PDF

    EP9122

    Abstract: EP9100 EP9101 EP9102 EP9103 EP9104 EP9105 EP9106 EP9107 EP9115
    Text: SMD 28 Pin 5 Tap TTL Compatible Active Delay Lines Delays are ±5% or ±2 nS† Tap Total 5, 10, 15, 20 6, 12, 18, 24 7, 14, 21, 28 8, 16, 24, 32 9, 18, 27, 36 10, 20, 30, 40 12, 24, 36, 48 15, 30, 45, 60 J-Lead P/N 25 30 35 40 45 50 60 75 †Whichever is greater.


    Original     		EP9100 EP9101 EP9102 EP9103 EP9104 EP9105 EP9106 EP9107 EP9115 EP9116 EP9122 EP9100 EP9101 EP9102 EP9103 EP9104 EP9105 EP9106 EP9107 EP9115 PDF

    EP-912

    Abstract: EP9100
    Text: SMD 28 Pin 5 Tap TTL Compatible Active Delay Lines J-Lead P/N Delays are ±5% or ±2 nS Tap Total 5, 10, 15, 20 6, 12, 18, 24 7 ,1 4,2 1 ,2 8 8, 16,24,32 9, 18, 27,36 10,20, 30,40 12, 24, 36, 48 15,30, 45,60 EP9100 EP9101 EP9102 EP9103 EP9104 EP9105 EP9106


    OCR Scan     		EP9100 EP9101 EP9102 EP9103 EP9104 EP9105 EP9106 EP9107 EP9115 EP9116 EP-912 PDF

    Untitled

    Abstract: No abstract text available
    Text: SMD 28 Pin 5 Tap TTL Compatible Active Delay Lines J-Lead P/N Delays are ±5% or ±2 nSt Tap Total 5, 10, 15, 20 6 , 12, 18, 24 7 ,1 4 ,2 1 ,2 8 8 ,1 6 ,2 4 , 32 9, 18, 27, 36 10, 20, 30, 40 12, 24, 36, 48 15, 30, 45, 60 EP9100 EP9101 EP9102 EP9103 EP9104


    OCR Scan     		EP9100 EP9101 EP9102 EP9103 EP9104 EP9105 EP9106 EP9107 EP9115 EP9116 PDF

    Untitled

    Abstract: No abstract text available
    Text: SMD 28 Pin 5 Tap TTL Compatible Active Delay Lines Delays are ±5% or ±2 nS Tap Total 25 30 35 40 45 50 60 75 5 ,1 0,1 5 ,2 0 6,12,18, 24 7,1 4,2 1 ,2 8 8,16, 24, 32 9,18, 27,36 10,20,30,40 12,24, 36,48 15,30,45,60 Gull-Wing P/N J-Lead P/N EP9100 EP9101 EP9102


    OCR Scan     		EP9100 EP9101 EP9102 EP9103 EP9104 EP9105 EP9106 EP9107 EP9115 EP9116 PDF

    EP9122

    Abstract: circuit ep9100 smd 57b EP9100 EP9101 EP9102 EP9108 EP9109 EP9110 EP9115
    Text: SMD 28 Pin 5 Tap TTL Compatible Active Delay Lines Delays are ±5% or +2 nSt Tap Total 5, 10, 15, 20 6, 12, 18, 24 7, 14, 21, 28 8, 16, 24, 32 9, 18, 27, 36 10, 20, 30, 40 12, 24, 36, 48 15, 30, 45, 60 J-Lead P/N 25 30 35 40 45 50 60 75 t Whichever is greater.


    OCR Scan     		EP9100 EP9115 EP9108 EP9123 EP9101 EP9116 EP9109 EP9124 EP9102 EP9117 EP9122 circuit ep9100 smd 57b EP9110 PDF

    EP610-25

    Abstract: programmer EPLD EP1810 EP610 EP910 ep910 programmer QLCC 24 EP6101-10
    Text: Classic E P L D F a m ily Ja n u a ry 1098, ve r 4 Features Data Sheet • ■ ■ ■ ■ ■ ■ ■ ■ ■ C om plete device fam ily w ith logic densities o f 300 to 9 X usable gates (see Table 1) D evice e ra su re an d reprogram m ing w ith advanced, non-volatile


    OCR Scan     		of300 EP1810 68-pin EP610-25 programmer EPLD EP610 EP910 ep910 programmer QLCC 24 EP6101-10 PDF

    EP910

    Abstract: altera EP910
    Text: EP910 EPLD Features • ■ ■ ■ ■ ■ High-performance, 24-macrocell Classic EPLD Combinatorial speeds with tPD as low as 12 ns Counter frequencies of up to 100 MHz Pipelined data rates of up to 100 MHz Programmable I/O architecture with up to 36 inputs or 24 outputs


    OCR Scan     		EP910 24-macrocell EP910, EP910T, EP910I 44-pin 40-pin 24-bit altera EP910 PDF

    P6102

    Abstract: EP6101-10
    Text: Classic EPLD Family J a n u ary 1998. v er. J Features Data S h e e t • ■ ■ ■ ■ ■ ■ ■ ■ ■ Complete device family w ith logic densities of 300 to 900 usable gates see Table 1 Device erasure and reprogram m ing w ith advanced, non-volatile


    OCR Scan     		PDF

    EP9122

    Abstract: smd 57b EP9100 EP9101 EP9102 EP9108 EP9109 EP9110 EP9115 EP9116
    Text: SMD 28 Pin 5 Tap TTL Compatible Active Delay Lines Delays are ±5% or +2 nSt Tap Total 5, 10, 15, 20 6, 12, 18, 24 7, 14, 21, 28 8, 16, 24, 32 9, 18, 27, 36 10, 20, 30, 40 12, 24, 36, 48 15, 30, 45, 60 J-Lead P/N 25 30 35 40 45 50 60 75 t Whichever is greater.


    OCR Scan     		EP9100 EP9115 EP9108 EP9123 EP9101 EP9116 EP9109 EP9124 EP9102 EP9117 EP9122 smd 57b EP9110 PDF

    TD 265 N 600 KOC

    Abstract: core i5 520 Scans-049 camtex trays sii Product Catalog EPM9560 film hot BT 342 project TIL Display 7160S
    Text: 1996 Data Book Data Book June 1996 A-DB-0696-01 Altera, MAX, M A X+PLUS, FLEX, FLEX 10K, FLEX 8000, FLEX 8000A, MAX 9000, MAX 7000, MAX 7000E, MAX 7000S, FLASHlogic, MAX 5000, Classic, M AX+PLUS II, PL-ASAP2, PLDshell Plus, FastTrack, AHDL, MPLD, Turbo Bit, BitBlaster, PENGN, RIPP 10, PLS-ES, ClockLock, ClockBoost,


    OCR Scan     		-DB-0696-01 7000E, 7000S, EPF10K100, EPF10K70, EPF10K50, EPF10K40, EPF10K30, EPF10K20, EPF10K10, TD 265 N 600 KOC core i5 520 Scans-049 camtex trays sii Product Catalog EPM9560 film hot BT 342 project TIL Display 7160S PDF

    EP610

    Abstract: ep910 programmer TI EP610 EP610-25 EP1810 EP910 ALTERA MAX 5000 programming EP6101-10
    Text: Classic EPLD Family January 1998. ver. 4 Features Data Sheet • ■ ■ ■ ■ ■ ■ ■ ■ ■ Complete device family w ith logic densities of 300 to 900 usable gates see Fable 1 Device erasure and reprogram m ing w ith advanced, non-volatile EPROM configuration elements


    OCR Scan     		EP1810 68-pin EP610 ep910 programmer TI EP610 EP610-25 EP910 ALTERA MAX 5000 programming EP6101-10 PDF

    Untitled

    Abstract: No abstract text available
    Text: SMD 28 Pin 5 Tap TTL Compatible Active Delay Lines - - 5, 10, 15,20 6, 12, 18, 24 7, 14, 21,28 8,16, 24, 32 9, 18, 27, 36 10, 20, 30, 40 12, 24,36, 48 15, 30,45, 60 Gull-Wing P/N J-Lead P/N Delays are ±5% or ±2 nS


    OCR Scan     		EP9100 EP9101 EP9102 EP9103 EP9104 EP9105 EP9106 EP9107 EP9115 EP9116 PDF

    ALTERA MAX 5000 programming

    Abstract: EP910-t altera EP910 24-MACROCELL osbt
    Text: EP910 EPLD • Features ■ ■ ■ ■ ■ High-performance, 24-macrocell Classic EPLD Com binatorial speeds with t PD as low as 12 ns - Counter frequencies of up to 100 MHz - Pipelined data rates of up to 100 MHz Program m able I/O architecture with up to 36 inputs or 24 outputs


    OCR Scan     		EP910 24-macrocell EP910, EP910T, EP910I 44-pin 40-pin 24-bit ALTERA MAX 5000 programming EP910-t altera EP910 osbt PDF

    P9101

    Abstract: 3721d
    Text: EP910 E P LD Features • ■ ■ ■ ■ ■ High-performance, 24-macrocell Classic EPLD Combinatorial speeds with tPD as fast as 12 ns Counter frequencies of up to 76.9 MHz Pipelined data rates of up to 125 MHz Programmable I/O architecture with up to 36 inputs or 24 outputs


    OCR Scan     		EP910 24-macrocell EP910I 44-pin 40-pin 24-bit P9101 3721d PDF

    altera ep900i

    Abstract: IC MSI ADDER
    Text: EP910 EPLD Features High-performance, 24-macrocell Classic EPLD Combinatorial speeds with tPD as low as 12 ns Counter frequencies of up to 76.9 MHz Pipelined data rates of up to 125 MHz Programmable I/O architecture with up to 36 inputs or 24 outputs EP910, EP910I, and EP900I devices that are pin-, function, and


    OCR Scan     		EP910 24-macrocell EP910, EP910I, EP900I 44-pin 40-pin 24-bit altera ep900i IC MSI ADDER PDF

    altera EP9101

    Abstract: ALTERA MAX 5000 programming altera ep910i
    Text: E P 9 1 0 E P LD Features • ■ ■ ■ ■ ■ High-performance, 24-macrocell Classic EPLD Combinatorial speeds with tPD as fast as 12 ns Counter frequencies of up to 76.9 MHz Pipelined data rates of up to 125 MHz Programmable I/O architecture with up to 36 inputs or 24 outputs


    OCR Scan     		24-macrocell EP910 EP910I 44-pin 40-pin 24-bit altera EP9101 ALTERA MAX 5000 programming altera ep910i PDF

    altera EP9101

    Abstract: No abstract text available
    Text: EP910EPLD Features • ■ ■ ■ ■ ■ High-performance, 24-macrocell Classic EPLD - Combinatorial speeds with t P D as fast as 12 ns Counter frequencies of up to 76.9 MHz Pipelined data rates of up to 125 MHz Programmable I/O architecture with up to 36 inputs or 24 outputs


    OCR Scan     		EP910EPLD 24-macrocell EP910 EP9101 44-pin 40-pin EP910I 24-bit altera EP9101 PDF

    altera EP910I

    Abstract: EP910-T EP910i EP910 Altera Classic EPLDs
    Text: E P 910 E P L D Features • ■ ■ ■ ■ ■ High-performance, 24-macrocell Classic EPLD Combinatorial speeds with tPD as low as 12 ns Counter frequencies of up to 100 MHz Pipelined data rates of up to 100 MHz Programmable I/O architecture with up to 36 inputs or 24 outputs


    OCR Scan     		24-macrocell EP910, EP910T, EP910I 44-pin 40-pin 24-bit altera EP910I EP910-T EP910 Altera Classic EPLDs PDF

    smd J225

    Abstract: J225 EP9122 J2-25 EP9101
    Text: SMD 28 Pin 5 Tap TTL Compatible Active Delay Lines J-Lead P/N Delays are ±5% or ±2 nSt Tap Total 5, 10, 15, 20 6, 12, 18, 24 7, 14, 21, 28 8, 16, 24, 32 9, 18, 27, 36 10, 20, 30, 40 12, 24, 36, 48 15, 30, 45, 60 t Whichever is greater. Gull-Wing P/N EP9100


    OCR Scan     		EP9100 EP9115 EP9108 EP9123 EP9101 EP9116 EP9109 EP9124 EP9102 EP9117 smd J225 J225 EP9122 J2-25 PDF