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    EP1810 Search Results

    EP1810 Result Highlights (2)

    Part ECAD Model Manufacturer Description Download Buy
    EP1810LC-35 Rochester Electronics LLC EP1810 - Classic Family EPLD, Logic, 900 Gates, 48 Macrocells, 35ns, Commercial Visit Rochester Electronics LLC Buy
    EP1810GC-35 Rochester Electronics LLC EP1810 - Classic Family EPLD, Logic, 900 Gates, 48 Macrocells, 35ns, Commercial Visit Rochester Electronics LLC Buy
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    EP1810 Price and Stock

    Rochester Electronics LLC EP1810LC-35

    OT PLD, 40NS, CMOS, PQCC68
    Distributors Part Package Stock Lead Time Min Order Qty Price Buy
    DigiKey EP1810LC-35 Bulk 1,441 2
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    Rochester Electronics EP1810LC-35 1,441 1
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    Rochester Electronics LLC EP1810LI-45

    OT PLD, 50NS, CMOS, PQCC68
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    DigiKey EP1810LI-45 Bulk 1,317 2
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    Rochester Electronics EP1810LI-45 1,317 1
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    Rochester Electronics LLC EP1810LI-35

    OT PLD, 35NS, PQCC68
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    DigiKey EP1810LI-35 Bulk 230 2
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    Rochester Electronics EP1810LI-35 1,974 1
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    • 1000 $152.36
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    Rochester Electronics LLC EP1810GI-45

    UV PLD, 50NS, CMOS, CPGA68
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    DigiKey EP1810GI-45 Bulk 67 2
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    Rochester Electronics EP1810GI-45 67 1
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    Hammond Manufacturing IMEP1810

    TOOLS / EQUIPMENT
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    EP1810 Datasheets (34)

    Part ECAD Model Manufacturer Description Curated Datasheet Type PDF
    EP1810 Altera User Configurable Logic Data Book Scan PDF
    EP1810-20 Altera High-performance, 48-macrocell Classic EPLD Original PDF
    EP1810-20 Altera Classic EPLD Family Scan PDF
    EP1810-20 Altera High-performance 48-macrocell Devices Scan PDF
    EP1810-20CPGA68 Altera SPLD Original PDF
    EP1810-20PLCC68 Altera SPLD Original PDF
    EP1810-25 Altera High-performance, 48-macrocell Classic EPLD Original PDF
    EP1810-25 Altera Classic EPLD Family Scan PDF
    EP1810-25 Altera High-Performance 48-Macrocell Devices Scan PDF
    EP1810-25CPGA68 Altera SPLD Original PDF
    EP1810-25PLCC68 Altera SPLD Original PDF
    EP1810-35 Altera High-performance, 48-macrocell Classic EPLD Original PDF
    EP1810-35 Altera Classic EPLD Family Scan PDF
    EP1810-35 Altera High-Performance 48-Macrocell Devices Scan PDF
    EP1810-35CPGA68 Altera SPLD Original PDF
    EP1810-35PLCC68 Altera SPLD Original PDF
    EP1810-45 Altera High-performance, 48-macrocell Classic EPLD Original PDF
    EP1810-45 Altera Classic EPLD Family Scan PDF
    EP1810-45 Altera High-Performance 48-Macrocell Devices Scan PDF
    EP1810-45CPGA68 Altera SPLD Original PDF

    EP1810 Datasheets Context Search

    Catalog Datasheet Type Document Tags PDF

    shiftregisters

    Abstract: EP910 altera TTL library 74LS series logic gates 74LS EP1810 EP1810-45 EP610 PLE40 altera logicaps TTL library
    Text: EP1810 Y 7 \ m HIGH PERFORMANCE 4 8 MACROCELL EPLD m 10 I U FEATURES GENERAL DESCRIPTION • Erasable, User-Configurable LSI circuit capable of implementing 2100 equivalent gates of conven­ tional and custom logic. • Speed equivalent to 74LS TTL with 33 MHz clock


    OCR Scan     		PDF

    EPM5128LC

    Abstract: epm5128jc MPM5128LC
    Text: MPLDs Mask-Programmed Logic Devices Data Sheet September 1991, ver. 1 □ □ □ Features □ □ □ □ □ □ General Description Masked versions of EPLD designs Reduced cost for large-volume applications Available for EP1810, EPM5032, EPM5064, EPM5128, EPM5130,


    OCR Scan     		EP1810, EPM5032, EPM5064, EPM5128, EPM5130, EPM5192, EPS464 EPM5128LC epm5128jc MPM5128LC PDF

    Untitled

    Abstract: No abstract text available
    Text: EP1810T EPLD Features □ □ □ □ General Description Altera's EP1810T Erasable Programmable Logic Device EPLD is a lowcost, high-performance version of the EP1810 device. This EPLD operates in a turbo mode that is optimized for high-speed applications. The Turbo


    OCR Scan     		EP1810T EP1810 68-pin EP1810-20T, EP1810-25T, EP1810-35T PDF

    Altera EP1810

    Abstract: No abstract text available
    Text: ALTERA CORP 47E D • 05*15372 DQ0211b 376 ■ ALT T ^ to -o / EP1810 EPLD s A N b [m □ □ □ □ □ □ □ □ □ □ High-density replacement for TTL and 74HC High-performance 48-macrocell EPLD with tPD = 20 ns and counter frequencies up to 50 MHz


    OCR Scan     		000211b EP1810 48-Macrocell EP1830-20, EP1830-25, EP1830-30 EP1830-25 EP1830 Altera EP1810 PDF

    MIL-STD-883-compliant

    Abstract: pipelined adder
    Text: EP1810 EPLD High-performance, 48-macrocell Classic EPLD Combinatorial speeds with t PD as low as 20 ns - Counter frequencies of up to 50 MHz - Pipelined data rates of up to 62.5 MHz Programmable I/O architecture with up to 64 inputs or 48 outputs The following devices are pin-, function-, and programming filecompatible: EP1810, EP1810T, and EP1810 MIL-STD-883-compliant


    OCR Scan     		EP1810 48-macrocell EP1810, EP1810T, MIL-STD-883-compliant 68-pin pipelined adder PDF

    ALTERA EP1810LC-45

    Abstract: EP1810LC-45 EP1810LC-35 EP1810JC-45 EP1810jC-35 EP1810JC EP1810LC45
    Text: EP1810 HIGH-PERFORMANCE 48-MACROCELL ERASABLE PROGRAMMABLE LOGIC DEVICE EPLD D3232. FEBRUARY 1989-R E V IS E D AUGUST 1989 • Erasable, User-Configurable LSI Circuit Capable of Implementing 2100 Equivalent Gates of Conventional and Custom Logic CHIP-CARRIER PACKAGE


    OCR Scan     		EP1810 48-MACROCELL D3232. 1989-R 33-MHz ALTERA EP1810LC-45 EP1810LC-45 EP1810LC-35 EP1810JC-45 EP1810jC-35 EP1810JC EP1810LC45 PDF

    Untitled

    Abstract: No abstract text available
    Text: Classic EPLD Family June 1996, ver. 3 Features Data Sheet • ■ ■ ■ ■ ■ ■ ■ ■ Table 1. Classic Device Features Feature EP1810 900 300 450 16 24 48 Maximum user I/O pins 22 38 64 tp D n s 10 12 20 100 76.9 50 f CNT A-DS-CLASSIC-03 EP910 &


    OCR Scan     		PDF

    Untitled

    Abstract: No abstract text available
    Text: EP1810 EPLD Features □ Ü □ J General Description The EP1810 Erasable Programmable Logic Device E P L D offers L S I density, TTL-equivalent speed, and low power consumption. It is available in 68-pin w ind ow ed ceramic and O T P plastic j-lead chip carrier and w indow ed


    OCR Scan     		EP1810 48-macrocell EP1810T EP1830 68-pin EP1810-20 PDF

    ALTERA EP

    Abstract: I7232 MIL-STD-883-compliant
    Text: EP1810 EPLD Features • High-performance, 48-macrocell Classic EPLD Combinatorial speeds with tPD as low as 20 ns Counter frequencies of up to 50 MHz Pipelined data rates of up to 62.5 MHz Programmable I/O architecture with up to 64 inputs or 48 outputs The following devices are pin-, function-, and programming filecompatible: EP1810, EP1810T, and EP1810 MIL-STD-883-compliant


    OCR Scan     		EP1810 48-macrocell EP1810, EP1810T, MIL-STD-883-compliant 68-pin ALTERA EP I7232 PDF

    48-MACROCELL

    Abstract: No abstract text available
    Text: EP1810 EPLD Features ^ High-performance, 48-macrocell Classic EPLD Combinatorial speeds with tPD = 20,25,35, and 45 ns Counter frequencies up to 50 MHz Pipelined data rates up to 62.5 MHz Programmable I/O architecture with up to 64 inputs or 48 outputs Pin-, function-, and programming file-compatible with Altera's


    OCR Scan     		EP1810 48-macrocell EP1810T MIL-STD-883-compliant 68-pin ALTED001 PDF

    EP600 programming

    Abstract: ple3-12a Altera EP1800 EPS448 PLE3-12 EP610 ORDERING ep1800 EP600 altera ep900 PLED448
    Text: PLED/J/G P L 1 D /J/G PROGRAMMING ADAPTORS PLED/J/G FEATURES GENERAL DESCRIPTION • Programming adaptors for Altera EPS448, EP600/ EP610, EP900/EP910, EP1210, EPB1400 and EP1800/ EP1810 EPLDs. The Altera PLED/J/G 448, 600, 900, 1210, 1400 and 1800 are enhancement products allowing device pro­


    OCR Scan     		EPS448, EP600/ EP610, EP900/EP910, EP1210, EPB1400 EP1800/ EP1810 PLE3-12 EPS448 EP600 programming ple3-12a Altera EP1800 EP610 ORDERING ep1800 EP600 altera ep900 PLED448 PDF

    Untitled

    Abstract: No abstract text available
    Text: EP1830 EPLD Features □ □ General Description Altera's EP1830 Erasable Programmable Logic Device EPLD is a fast, low-power version of the EP1810 device. The EP1830 can implement four 12-bit counters at up to 50 MHz and typically consumes 20 mA when operating at 1 MHz. The EP1830 EPLD is available in OTP plastic 68-pin


    OCR Scan     		EP1830 EP1810 12-bit 68-pin EP1830-20, EP1830-25, PDF

    Altera EP1810

    Abstract: MIL-STD-883-compliant
    Text: EP1810 MIL-STD-883-Compliant EPLD Features □ □ □ □ □ High-performance, 48-macrocell Classic EPLD Combinatorial speeds with tPD = 45 ns Counter frequencies up to 22.2 MHz Pipelined data rates up to 33.3 MHz Programmable I/O architecture with up to 20 inputs or 16 outputs


    OCR Scan     		EP1810 MIL-STD-883-Compliant 48-macrocell EP1810T 68-pin ALTED001 Altera EP1810 PDF

    Untitled

    Abstract: No abstract text available
    Text: ANbrt r*a\ EP1810 EPLDs High-Performance 48-Macrocell Devices September 1991, ver. 2 Features Data Sheet □ □ □ □ □ □ □ □ □ □ General Description tPD The EP1810 Erasable Program m able Logic Devices E P L D s offer L S I density, TTL-equivalent speed, and low power consumption. Each E P L D can


    OCR Scan     		EP1810 48-Macrocell programEP1810 PDF

    Signal Path Designer

    Abstract: No abstract text available
    Text: Classic EPLD Family J a n u a ry 1998. ver. Features Data Sheet 4 * • ■ ■ ■ ■ ■ ■ ■ Table 1. Classic Device Features EP610 EP610I EP910 EP910I EP1810 300 450 900 Macrocells 16 24 48 Maximum user I/O pins 22 38 64 Feature Usable gates Altera Corporation


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    C2657

    Abstract: EPI810 K102-8 EP181B
    Text: EP1810 EPLD Features • ■ ■ ■ ■ High-performance, 48-macrocell Classic EPLD Combinatorial speeds with tPD as fast as 20 ns - Counter frequencies of up to 50 MHz - Pipelined data rates of up to 62.5 MHz Programmable I/O architecture with up to 64 inputs or 48 outputs


    OCR Scan     		EP1810 48-macrocell 68-pin C2657 EPI810 K102-8 EP181B PDF

    EP1810-XXT

    Abstract: No abstract text available
    Text: EP 1810T EPLD Features □ LI □ □ General Description A ltera's EP1810T E rasab le P ro g ram m ab le Logic D evice EPLD is a lowcost, h igh -p erform an ce version of the EP1810 d evice. T h is EP LD o p erate s in a turbo m od e that is op tim ized for h igh -sp eed ap p lication s. The T urbo


    OCR Scan     		1810T EP1810 EP1830 68-pin, EP1810T EP1810-20T, EP1810-25T, EP1810-35T EP1810-XXT PDF

    48 pin clcc footprint

    Abstract: chipmaster 3000 CLCC 64 pins footprint
    Text: PA1800-68 Z 68 pin PLCC socket/40 pin DIP 0.6" plug Supported Device/Footprints Adapter Wiring Using this adapter, the EP1810 in PLCC or CLCC package can be programmed on the EE Tools AllMax or Logical Devices ChipMaster 2000 & 3000 40 pin DIP programmers.


    Original     		PA1800-68 socket/40 EP1810 EP1810 PA1800-68 PA1800-68Z 48 pin clcc footprint chipmaster 3000 CLCC 64 pins footprint PDF

    EP1830

    Abstract: EP1810 jedec 74HC EP1810 EP18302 EP1830 jedec
    Text: EP1810 EPLDs High-Performance 48-Macrocell Devices Data Sheet September 1991, ver. 2 Features □ □ □ □ □ □ □ Q General Description The EP1810 Erasable Programmable Logic Devices EPLDs offer LSI density,TTL-equivalentspeed, and low power consumption. Each EPLD can


    OCR Scan     		EP1810 48-Macrocell EP1830-20, EP1830-25, EP1830-30 EP1830-25 EP1830 EP1810 jedec 74HC EP18302 EP1830 jedec PDF

    EP1810JC-35

    Abstract: programming manual EP910 EP1810LC-35 OLC-45 EP1810JC35 programming manual EPLD EP1810LI-45 EP1810JC EP1810I Erasable Programmable Logic Device
    Text: EP1810 HIGH-PERFORMANCE 48-MACROCELL ERASABLE PROGRAMMABLE LOGIC DEVICE EPLD D3232. FEBHUARY 1989-REVISED AUGUST 1989 CHIP-CARRIER PACKAGE Erasable, U ser-Configurable LSI Circuit C apable of Implementing 2100 Equivalent Gates of Conventional and Custom Logic


    OCR Scan     		EP1810 48-MACROCELL D3232. 1989-REVISED 33-MHz 68-pin 28Cll EP1810JC-35 programming manual EP910 EP1810LC-35 OLC-45 EP1810JC35 programming manual EPLD EP1810LI-45 EP1810JC EP1810I Erasable Programmable Logic Device PDF

    IOG11

    Abstract: H10IO K1026
    Text: AL TE RA CORP bäE » • D S R S 3 7 S Ü Ü G B M O R Û7Ô ALT EP1810 EPLD Features ^ □ □ □ □ □ High-performance, 48-macrocell Classic EPLD Combinatorial speeds with tPD = 20,25,35, and 45 ns Counter frequencies up to 50 MHz Pipelined data rates up to 62.5 MHz


    OCR Scan     		SRS37S EP1810 48-macrocell EP1810T MIL-STD-883-compliant 68-pin IOG11 H10IO K1026 PDF

    EP1800

    Abstract: Altera EP1800 Altera EP1810 EP1800 LOGIC DIAGRAM ICE3 48-MACROCELL EP1810 EPI800
    Text: EP1800 WMA 48-M ACROCELL EPLD EPI800 FEATURES GENERAL DESCRIPTION • High density, User-Configurable LSI log ic re­ placem ent for conventional and custom logic • Functional and pin com patible with the Altera EP1810 • 20 M H z clo ck rates • “Zero Pow er” typically 35 //A standby


    OCR Scan     		48-MACROCELL EP1810 250ns 100ns) EP1800-2 EP1800-3 EP1800 EP1800 Altera EP1800 Altera EP1810 EP1800 LOGIC DIAGRAM ICE3 EP1810 EPI800 PDF

    PDN0102

    Abstract: EP910LC EP1810LC-45H PDN01
    Text: PRODUCT DISCONTINUANCE NOTICE SELECTED CLASSIC DEVICES Altera will be discontinuing selected Classic family devices shown below . Discontinued Ordering Codes EP910ILC-15H EP910LC-40H EP1810LC-45H EP1810LC-35H C.F. – Call Factory Compatible Substitute C.F.


    Original     		EP910ILC-15H EP910LC-40H EP1810LC-45H EP1810LC-35H PDN0102 PDN0102 EP910LC EP1810LC-45H PDN01 PDF

    EP1810JC-45

    Abstract: logicaps schematic capture manual programming manual EP910 Flip flop JK cmos
    Text: EP1810 HIGH-PERFORMANCE 48-MACROCELL ERASABLE PROGRAMMABLE LOGIC DEVICE EPLO D3232, FEB RU ARY 1 9 8 9 -R E V IS E D AU GU ST 1989 • Erasable, User-Configurable LSI Circuit Capable of Implementing 2100 Equivalent Gates of Conventional and Custom Logic


    OCR Scan     		EP1810 48-MACROCELL D3232, 33-MHz EP1810JC-45 logicaps schematic capture manual programming manual EP910 Flip flop JK cmos PDF