EMRS1 Search Results

K4T51043QB-GCCC

Abstract: K4T51043QB-GCE6 K4T51043QB-GLE6
Contextual Info: Preliminary DDR2 SDRAM 512Mb B-die DDR2 SDRAM 512Mb B-die DDR2 SDRAM Specification Version 0.91 September 2003 Rev. 0.91 Sep. 2003 Page 1 of 38 Preliminary DDR2 SDRAM 512Mb B-die DDR2 SDRAM Contents 1. Key Feature 2. Package Pinout/Mechnical Dimension & Addressing

DFSDM

Abstract: SAM9M10 K 2141 AC97 ARM926EJ-S AT91SAM ISO7816 NBC 3111 hc 541 rfid reader id-20
Contextual Info: Features • 400 MHz ARM926EJ-S ARM Thumb® Processor – 32 KBytes Data Cache, 32 KBytes Instruction Cache, MMU • Memories • • • • – DDR2 Controller 4-bank DDR2/LPDDR, SDR/LPSDR – External Bus Interface supporting 4-bank DDR2/LPDDR, SDR/LPSDR, Static

Contextual Info: E-Series Surface Mount Mixer 1600 - 2300 MHz EMRS-1800 V3.00 Features ● ● ● SM-24 LO Power +17 dBm Up to +14 dBm RF Surface Mount Specifications @ 25°C Frequency Range RF LO IF 1600 - 2300 MHz 1600 - 2300 MHz 10 - 200 MHz Conversion Loss dB 1600 - 2300 MHz

Contextual Info: ARM-based Embedded MPU SAM9G35 DATASHEET Description The SAM9G35 is a member of the Atmel series of 400 MHz ARM926EJ-S embedded MPUs that support high bandwidth communication and advanced user interfaces and are optimized for industrial applications such as building automation,

MT47H128M8CF-25

Abstract: 8 resistor array 10k smd 103
Contextual Info: 1Gb: x8, x16 Automotive DDR2 SDRAM Features Automotive DDR2 SDRAM MT47H128M8 – 16 Meg x 8 x 8 banks MT47H64M16 – 8 Meg x 16 x 8 banks Options1 Features • • • • • • • • • • • • • • • • • • • Marking • Configuration

k4n26323ae

Abstract: K4N26 K4N26323AE-GC20 K4N26323AE-GC22 K4N26323AE-GC25
Contextual Info: 128M GDDR2 SDRAM K4N26323AE-GC 128Mbit GDDR2 SDRAM 1M x 32Bit x 4 Banks GDDR2 SDRAM with Differential Data Strobe and DLL Revision 1.7 January 2003 Samsung Electronics reserves the right to change products or specification without notice. - 1 - Rev. 1.7 Jan. 2003

Contextual Info: 2Gb: x8, x16 Automotive DDR2 SDRAM Features Automotive DDR2 SDRAM MT47H256M8 – 32 Meg x 8 x 8 banks MT47H128M16 – 16 Meg x 16 x 8 banks Options1 Features • • • • • • • • • • • • • • • • • • • • Marking • Configuration

Contextual Info: PRELIMINARY V59C1G01 408/808/168 QA HIGH PERFORMANCE 1Gbit DDR2 SDRAM 8 BANKS X 32Mbit X 4 (408) 8 BANKS X 16Mbit X 8 (808) 8 BANKS X 8Mbit X 16 (168) 3 25A 25 19A DDR2-667 DDR2-800 DDR2-800 DDR2-1066 Clock Cycle Time (tCK3) 5ns 5ns 5ns 5ns Clock Cycle Time (tCK4)

Contextual Info: PRELIMINARY V59C1512 404/804/164 QA HIGH PERFORMANCE 512 Mbit DDR2 SDRAM 4 BANKS X 32Mbit X 4 (404) 4 BANKS X 16Mbit X 8 (804) 4 BANKS X 8Mbit X 16 (164) 5 37 3 DDR2-400 DDR2-533 DDR2-667 Clock Cycle Time (tCK3) 5ns 5ns 5ns Clock Cycle Time (tCK4) 5ns 3.75ns

Contextual Info: V59C1G02168QBP HIGH PERFORMANCE 2Gbit DDR2 SDRAM 8 BANKS X 16Mbit X 16 3 25A 25 DDR2-667 DDR2-800 DDR2-800 Clock Cycle Time tCK3 5ns 5ns 5ns Clock Cycle Time (tCK4) 3.75ns 3.75ns 3.75ns Clock Cycle Time (tCK5) 3ns 3ns 2.5ns Clock Cycle Time (tCK6) 3ns 2.5ns

Contextual Info: PRELIMINARY V59C1512 404/804/164 QB HIGH PERFORMANCE 512 Mbit DDR2 SDRAM 4 BANKS X 32Mbit X 4 (404) 4 BANKS X 16Mbit X 8 (804) 4 BANKS X 8Mbit X 16 (164) 5 37 3 25A 25 DDR2-400 DDR2-533 DDR2-667 DDR2-800 DDR2-800 Clock Cycle Time (tCK3) 5ns 5ns 5ns 5ns 5ns

hyb18h1g321af-11

Abstract: qimonda hyb18h
Contextual Info: June 2007 HYB18H 1G 321 A F- 1 1 / 1 4 GDDR3 Graphics RAM 1-Gbit GDDR3 Graphics RAM RoHS compliant Data S heet Rev. 0.80 Data Sheet HYB18H1G321AF-11/14 1-Gbit GDDR3 HYB18H1G321AF-11/14 Preliminary Revision History: 2007-06, Rev. 0.80 Page Subjects major changes since last revision

Contextual Info: V59C1512 404/804/164 QD*I 512 Mbit DDR2 SDRAM, INDUSTRIAL TEMPERATURE 4 BANKS X 32Mbit X 4 (404) 4 BANKS X 16Mbit X 8 (804) 4 BANKS X 8Mbit X 16 (164) 5 37 3 25A 25 19A DDR2-400 DDR2-533 DDR2-667 DDR2-800 DDR2-800 DDR2-1066 Clock Cycle Time (tCK3) 5ns 5ns

Contextual Info: V59C1512 404/804/164 QC HIGH PERFORMANCE 512 Mbit DDR2 SDRAM 4 BANKS X 32Mbit X 4 (404) 4 BANKS X 16Mbit X 8 (804) 4 BANKS X 8Mbit X 16 (164) 5 37 3 25A 25 DDR2-400 DDR2-533 DDR2-667 DDR2-800 DDR2-800 Clock Cycle Time (tCK3) 5ns 5ns 5ns 5ns 5ns Clock Cycle Time (tCK4)

Contextual Info: V59C1G02168QBP HIGH PERFORMANCE 2Gbit DDR2 SDRAM 8 BANKS X 16Mbit X 16 3 25A 25 DDR2-667 DDR2-800 DDR2-800 Clock Cycle Time tCK3 5ns 5ns 5ns Clock Cycle Time (tCK4) 3.75ns 3.75ns 3.75ns Clock Cycle Time (tCK5) 3ns 3ns 2.5ns Clock Cycle Time (tCK6) - 2.5ns

HYB18H512321B2F-14

Contextual Info: March 2008 HYB18H512321B2F–12/14 GDDR3 Graphics RAM 512-Mbit GDDR3 Graphics RAM RoHS compliant Advance Internet Data Sheet Rev. 0.70 Advance Internet Data Sheet HYB18H512321B2F 512-Mbit GDDR3 HYB18H512321B2F–12/14 Revision History: 2008-03, Rev. 0.70 Page

9.1 b3

Contextual Info: V59C1256 404/804/164 QA*I HIGH PERFORMANCE 256Mbit DDR2 SDRAM, INDUSTRIAL TEMPERATURE 4 BANKS X 16Mbit X 4 (404) 4 BANKS X 8Mbit X 8 (804) 4 BANKS X 4Mbit X 16 (164) PRELIMINARY 37 3 25 DDR2-533 DDR2-667 DDR2-800 Clock Cycle Time (tCK3) 5ns 5ns 5ns Clock Cycle Time (tCK4)

Contextual Info: V59C1256 404/804/164 QI HIGH PERFORMANCE 256 Mbit DDR2 SDRAM 4 BANKS X 16Mbit X 4 (404) 4 BANKS X 8Mbit X 8 (804) 4 BANKS X 4Mbit X 16 (164) 37 3 25A 25 19A DDR2-533 DDR2-667 DDR2-800 DDR2-800 DDR2-1066 Clock Cycle Time (tCK3) 5ns 5ns 5ns 5ns 5ns Clock Cycle Time (tCK4)

Contextual Info: V59C1G01 808/168 QC HIGH PERFORMANCE 1Gbit DDR2 SDRAM 8 BANKS X 16Mbit X 8 (808) 8 BANKS X 8Mbit X 16 (168) 37 3 25A 25 19A DDR2-533 DDR2-667 DDR2-800 DDR2-800 DDR2-1066 Clock Cycle Time (tCK3) 5ns 5ns 5ns 5ns 5ns Clock Cycle Time (tCK4) 3.75ns 3.75ns 3.75ns

9.1 b3

Contextual Info: PRELIMINARY V59C1256 404/804/164 QA HIGH PERFORMANCE 256Mbit DDR2 SDRAM 4 BANKS X 16Mbit X 4 (404) 4 BANKS X 8Mbit X 8 (804) 4 BANKS X 4Mbit X 16 (164) 37 3 25A 25 DDR2-533 DDR2-667 DDR2-800 DDR2-800 Clock Cycle Time (tCK3) 5ns 5ns 5ns 5ns Clock Cycle Time (tCK4)

Contextual Info: V59C1512 404/804/164 QC*I 512 Mbit DDR2 SDRAM, INDUSTRIAL TEMPERATURE 4 BANKS X 32Mbit X 4 (404) 4 BANKS X 16Mbit X 8 (804) 4 BANKS X 8Mbit X 16 (164) 5 37 3 25A 25 DDR2-400 DDR2-533 DDR2-667 DDR2-800 DDR2-800 Clock Cycle Time (tCK3) 5ns 5ns 5ns 5ns 5ns Clock Cycle Time (tCK4)

W641GG2KB

Abstract: gddr3 schematic WBGA-136 W641GG2
Contextual Info: W641GG2KB 1-Gbit GDDR3 Graphics SDRAM Table of Contents 1. GENERAL DESCRIPTION . 6 2. FEATURES . 7

is46dr32801a-5bbla1

Abstract: 126-ball IS46DR32801A
Contextual Info: IS43DR32800A, IS43/46DR32801A 8Mx32 256Mb DDR2 DRAM FEATURES • Vdd = 1.8V ±0.1V, Vddq = 1.8V ±0.1V • JEDEC standard 1.8V I/O SSTL_18-compatible • Double data rate interface: two data transfers per clock cycle • Differential data strobe (DQS, DQS)

IS43DR83200A

Abstract: IS43DR16160A-3DBLI datasheet IS43DR16160A-37CBLI IS43DR83200A-37CBLI IS43DR32160A DDR2 x32
Contextual Info: IS43DR83200A IS43/46DR16160A, IS43DR32160A 32Mx8, 16Mx16, 16Mx32 stacked die DDR2 DRAM FEATURES • Vdd = 1.8V ±0.1V, Vddq = 1.8V ±0.1V • JEDEC standard 1.8V I/O (SSTL_18-compatible) • Double data rate interface: two data transfers per clock cycle