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Catalog Datasheet	Type	Document Tags	PDF
SEM 2005 16 PINS Abstract: pin diagram of sem 2005 CY7C138 CY7C139 sem 2005 16 pin 25j81 Contextual Info: CY7C138 CY7C1394K x 8/9 Dual-Port Static RAM with Sem, Int, Busy CY7C138 CY7C139 4K x 8/9 Dual-Port Static RAM with Sem, Int, Busy Features • True Dual-Ported memory cells that allow simultaneous reads of the same memory location • 4K x 8 organization CY7C138	Original	CY7C138 CY7C1394K CY7C138 CY7C139 CY7C138) CY7C139) 65-micron CY7C138/CY7C139 SEM 2005 16 PINS pin diagram of sem 2005 CY7C139 sem 2005 16 pin 25j81	PDF
Contextual Info:  CY7C1392KV18, CY7C1992KV18 CY7C1393KV18, CY7C1394KV18 18-Mbit DDR II SIO SRAM Two-Word Burst Architecture Features Functional Description • 18 Mbit density 2 M x 8, 2 M x 9, 1 M x 18, 512 K x 36 ■ 333-MHz clock for high bandwidth ■ Two-word burst for reducing address bus frequency	Original	CY7C1392KV18, CY7C1992KV18 CY7C1393KV18, CY7C1394KV18 18-Mbit 333-MHz	PDF
Contextual Info: CY7C1392KV18, CY7C1992KV18 CY7C1393KV18, CY7C1394KV18 18-Mbit DDR II SIO SRAM Two-Word Burst Architecture Features Functional Description • 18 Mbit density 2 M x 8, 2 M x 9, 1 M x 18, 512 K x 36 ■ 333-MHz clock for high bandwidth ■ Two-word burst for reducing address bus frequency	Original	CY7C1392KV18, CY7C1992KV18 CY7C1393KV18, CY7C1394KV18 18-Mbit CY7C1992KV18, CY7C1394KV18	PDF
SEM 2005 16 PINS Abstract: sem 2005 CY7C138 CY7C139 Contextual Info: CY7C138 CY7C1394K x 8/9 Dual-Port Static RAM with Sem, Int, Busy CY7C138 CY7C139 4K x 8/9 Dual-Port Static RAM with Sem, Int, Busy Features • True Dual-Ported memory cells that allow simultaneous reads of the same memory location • 4K x 8 organization CY7C138	Original	CY7C138 CY7C1394K CY7C138 CY7C139 CY7C138) CY7C139) 65-micron CY7C138/CY7C139 SEM 2005 16 PINS sem 2005 CY7C139	PDF
Contextual Info: CY7C1392KV18 CY7C1393KV18 18-Mbit DDR II SIO SRAM Two-Word Burst Architecture 18-Mbit DDR II SIO SRAM Two-Word Burst Architecture Features Configurations • 18-Mbit density 2 M x 8, 1 M × 18 CY7C1392KV18 – 2 M × 8 ■ 333-MHz clock for high bandwidth	Original	CY7C1392KV18 CY7C1393KV18 18-Mbit 333-MHz	PDF
Contextual Info: CY7C1392KV18 CY7C1393KV18 18-Mbit DDR II SIO SRAM Two-Word Burst Architecture 18-Mbit DDR II SIO SRAM Two-Word Burst Architecture Features Configurations • 18-Mbit density 2 M x 8, 1 M × 18 CY7C1392KV18 – 2 M × 8 ■ 333-MHz clock for high bandwidth	Original	CY7C1392KV18 CY7C1393KV18 18-Mbit CY7C1392KV18 333-MHz	PDF
Contextual Info: CY7C1392KV18 CY7C1393KV18 18-Mbit DDR II SIO SRAM Two-Word Burst Architecture 18-Mbit DDR II SIO SRAM Two-Word Burst Architecture Features Configurations • 18-Mbit density 2 M x 8, 1 M × 18 CY7C1392KV18 – 2 M × 8 ■ 333-MHz clock for high bandwidth	Original	CY7C1392KV18 CY7C1393KV18 18-Mbit CY7C1392KV18 333-MHz	PDF
Contextual Info: CY7C1392KV18 CY7C1393KV18 18-Mbit DDR II SIO SRAM Two-Word Burst Architecture 18-Mbit DDR II SIO SRAM Two-Word Burst Architecture Features Configurations • 18-Mbit density 2 M x 8, 1 M × 18 CY7C1392KV18 – 2 M × 8 ■ 333-MHz clock for high bandwidth	Original	CY7C1392KV18 CY7C1393KV18 18-Mbit 333-MHz	PDF