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    CY7C1392KV18 Price and Stock

    Rochester Electronics LLC CY7C1392KV18-250BZXC

    IC SRAM 16MBIT PARALLEL 165FBGA
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    DigiKey CY7C1392KV18-250BZXC Bulk 13
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    Flip Electronics CY7C1392KV18-250BZXC

    IC SRAM 16MBIT PAR 165FBGA
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    DigiKey CY7C1392KV18-250BZXC Tray 30
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    Infineon Technologies AG CY7C1392KV18-250BZXC

    IC SRAM 16MBIT PAR 165FBGA
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    Avnet Americas CY7C1392KV18-250BZXC Tray 0 Weeks, 2 Days 35
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    Rochester Electronics CY7C1392KV18-250BZXC 4 1
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    Cypress Semiconductor CY7C1392KV18-250BZXC

    SRAM Chip Sync Dual 1.8V 18M-bit 2M x 8 0.45ns 165-Pin FBGA Tray
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    Verical CY7C1392KV18-250BZXC 347 13
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    Rochester Electronics CY7C1392KV18-250BZXC 347 1
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    Flip Electronics CY7C1392KV18-250BZXC 1,060
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    CY7C1392KV18 Datasheets (1)

    Part ECAD Model Manufacturer Description Curated Datasheet Type PDF
    CY7C1392KV18-250BZXC Cypress Semiconductor Memory, Integrated Circuits (ICs), IC SRAM 16MBIT 250MHZ 165FBGA Original PDF

    CY7C1392KV18 Datasheets Context Search

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    Untitled

    Abstract: No abstract text available
    Text: CY7C1392KV18 CY7C1393KV18 18-Mbit DDR II SIO SRAM Two-Word Burst Architecture 18-Mbit DDR II SIO SRAM Two-Word Burst Architecture Features Configurations • 18-Mbit density 2 M x 8, 1 M × 18 CY7C1392KV18 – 2 M × 8 ■ 333-MHz clock for high bandwidth


    Original
    PDF CY7C1392KV18 CY7C1393KV18 18-Mbit 333-MHz

    Untitled

    Abstract: No abstract text available
    Text: CY7C1392KV18 CY7C1393KV18 18-Mbit DDR II SIO SRAM Two-Word Burst Architecture 18-Mbit DDR II SIO SRAM Two-Word Burst Architecture Features Configurations • 18-Mbit density 2 M x 8, 1 M × 18 CY7C1392KV18 – 2 M × 8 ■ 333-MHz clock for high bandwidth


    Original
    PDF CY7C1392KV18 CY7C1393KV18 18-Mbit CY7C1392KV18 333-MHz

    Untitled

    Abstract: No abstract text available
    Text: CY7C1392KV18 CY7C1393KV18 18-Mbit DDR II SIO SRAM Two-Word Burst Architecture 18-Mbit DDR II SIO SRAM Two-Word Burst Architecture Features Configurations • 18-Mbit density 2 M x 8, 1 M × 18 CY7C1392KV18 – 2 M × 8 ■ 333-MHz clock for high bandwidth


    Original
    PDF CY7C1392KV18 CY7C1393KV18 18-Mbit CY7C1392KV18 333-MHz

    Untitled

    Abstract: No abstract text available
    Text:  CY7C1392KV18, CY7C1992KV18 CY7C1393KV18, CY7C1394KV18 18-Mbit DDR II SIO SRAM Two-Word Burst Architecture Features Functional Description • 18 Mbit density 2 M x 8, 2 M x 9, 1 M x 18, 512 K x 36 ■ 333-MHz clock for high bandwidth ■ Two-word burst for reducing address bus frequency


    Original
    PDF CY7C1392KV18, CY7C1992KV18 CY7C1393KV18, CY7C1394KV18 18-Mbit 333-MHz

    Untitled

    Abstract: No abstract text available
    Text: CY7C1392KV18, CY7C1992KV18 CY7C1393KV18, CY7C1394KV18 18-Mbit DDR II SIO SRAM Two-Word Burst Architecture Features Functional Description • 18 Mbit density 2 M x 8, 2 M x 9, 1 M x 18, 512 K x 36 ■ 333-MHz clock for high bandwidth ■ Two-word burst for reducing address bus frequency


    Original
    PDF CY7C1392KV18, CY7C1992KV18 CY7C1393KV18, CY7C1394KV18 18-Mbit CY7C1992KV18, CY7C1394KV18

    Untitled

    Abstract: No abstract text available
    Text: CY7C1392KV18 CY7C1393KV18 18-Mbit DDR II SIO SRAM Two-Word Burst Architecture 18-Mbit DDR II SIO SRAM Two-Word Burst Architecture Features Configurations • 18-Mbit density 2 M x 8, 1 M × 18 CY7C1392KV18 – 2 M × 8 ■ 333-MHz clock for high bandwidth


    Original
    PDF CY7C1392KV18 CY7C1393KV18 18-Mbit 333-MHz