CLBL723 Search Results

74ACT11153

Abstract: 54act11153
Contextual Info: TEXAS INSTR 31E LOGIC 3> • Û clbl723 000^521 S ■ TII3 54ACT11153,74ACT11153 DUAL 1 OF 4 DATA SELECTORS/MULTIPLEXERS “T - U Inputs are TTL-Voltage Compatible 1 54ACT11153 . J PA C K A G E 74ACT11153 . D O R N PA C K A G E (TOP VIEW) Permits Multiplexing From N Lines to

Contextual Info: TEXAS INSTR 31E D LOGIC • Ô clbl723 GGfllSlH 1 ■ TII3 54AC11153,74AC11153 DUAL 1 OF 4 DATA SELECTORS/MULTIPLEXERS T ^ ( û - Z ì- 5 Ì D3582, JUNE 1990 54AC11153 . . . J PACKAGE 74AC11153 . . . D OR N PACKAGE (TOP VIEW) Permits Multiplexing From N Lines to

sf 127d

Abstract: 127D IC51-1324-828 SN74ABT3611 D103E
Contextual Info: SN74ABT3611 64 x 36 CLOCKED FIRST-IN, FIRST-OUT MEMORY SCBS127D - JULY 1992 - REVISED SEPTEMBER 1995 Free-Running CLKA and CLKB Can Be Asynchronous or Coincident 64 x 36 Clocked FIFO Buffering Data From Port A to Port B Mailbox-Bypass Register In Each Direction

Contextual Info: SN54ALS32, SN54AS32, SN74ALS32, SN74AS32 QUADRUPLE 2-INPUT POSITIVE-OR GATES S D A S 1 1 3 B - A P R IL 19 8 2 - R E V IS E D D E C E M B E R 1 9 9 4 • Package Options Include Plastic Small-Outline D Packages, Ceramic Chip Carriers (FK), and Standard Plastic (N) and

010530b

Abstract: 10B1 10B2 10B3 11B1 11B3 16B1 16B2 17B1 SN74CBT16214
Contextual Info: SN74CBT16214 3-T0-1 BUS-SELECT SWITCH S C D S 008G - MAY 1993 - R EVISED A U G U S T 1996 * 5-Q Switch Connection Between Two Ports 1 • TTL-Compatible Input and Output Levels • Package Options Include Plastic Thin Shrink Small-Outline DGG and 300-mil

AS146B

Contextual Info: SN54ALS29823, SN74ALS29823 9-BIT BUS-INTERFACE FLIP-FLOPS WITH 3-STATE OUTPUTS SDAS146B - JANUARY 1986 - R EVISED JANUARY 1995 Functionally Equivalent to AMD’s AM29823 Provide Extra Data Width Necessary for Wider Address/Data Paths or Buses With Parity Outputs Have Undershoot-Protectlon

SN74LV373

Contextual Info: SN74LV373 OCTAL TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS _ SCLS196A-FEBRUARY 1993- REVISED JULY 1995 DB, DW, OR PW PACKAGE CTOP VIEW • EPIC Enhanced-Performance Implanted CMOS) 2-n Process • Typical V o l p (Output Ground Bounce) < 0.8 V at VCc = 3.3 V, TA = 25°C