LBL723 Search Results

sf 127d

Abstract: 127D IC51-1324-828 SN74ABT3611 D103E
Contextual Info: SN74ABT3611 64 x 36 CLOCKED FIRST-IN, FIRST-OUT MEMORY SCBS127D - JULY 1992 - REVISED SEPTEMBER 1995 Free-Running CLKA and CLKB Can Be Asynchronous or Coincident 64 x 36 Clocked FIFO Buffering Data From Port A to Port B Mailbox-Bypass Register In Each Direction

74ACT16823

Abstract: D3955
Contextual Info: 74ACT16823 18-BIT BUS INTERFACE FLIP-FLOP WITH 3-STATE OUTPUTS SCAS16Q-D3955. APRIL 1991 -R EV IS ED APRIL 1993 * Member of the Texas Instruments Wldebus Family ' Packaged In Shrink Small-Outline 300-mil Package Using 25-mil Center-to-Center Pin Spacings

HAI 7203

Abstract: ACT8847 74ACT8847 SN74 multiplier
Contextual Info: TEXAS INSTR LOGIC SSE D 0^1723 GQÖS7G3 7 SN74ACT8847 64-Bit Floating Point Unit • Meets IEEE Standard for Single- and DoublePrecision Formats • Performs Floating Point and Integer Add, Subtract, Multiply, Divide, Square Root, and Compare • 64-Bit IEEE Divide in 11 Cycles, 64-Bit Square

SN74ALVC16843

Contextual Info: SN74ALVC16843 18-BIT BUS-INTERFACE D-TYPE LATCH WITH 3-STATE OUTPUTS S C A S275 - JA N U A R Y 1993 - REVISED M A RCH 1994 Member of the Texas Instruments Widebus Family DGG OR DL PACKAGE TOP VIEW Designed to Facilitate Incident-Wave Switching for Line Impedances of 50 Q

P34S8

Abstract: 74ACT11648
Contextual Info: 74ACT11648 OCTAL BUS TRANSCEIVER AND REGISTER WITH 3-STATE OUTPUTS SCAS115 - P34S8, MARCH 1990 - REVISED APRIL 1993 Inputs Are TTL-Voltage Compatible DW PACKAGE TOP VIEW Independent Registers A and B Buses _ J — o — u G [ 1 28 ] C A B Multiplexed Real-Time and Stored Data

fl inverter

Abstract: tl172 SN74LVU04
Contextual Info: SN74LVU04 HEX INVERTER S C L S 1 8 5 A - FEBRUARY 1993 - REVISED JULY 1995 • EPIC Enhanced-Performance Implanted CM O S 2 -ji Process D, DB, OR PW PACKAGE (TOP VIEW) » Typical V q l p (Output Ground Bounce) < 0.8 V at VCc = 3-3 V, TA = 25°C • Typical V q h v (Output V q h Undershoot)

Contextual Info: 74AC11652 OCTAL BUS TRANSCEIVER AND REGISTERS WITH 3-STATE OUTPUTS SCAS088A - DECEMBER 1989 - REVISED APRIL 1996 • Independent Registers and Enables for A and B Buses DW PACKAGE TOP VIEW • Multiplexed Real-Time and Stored Data • Inverting Data Paths

SN54AS250A

Contextual Info: SN54AS250A, SN74AS250A 1-0F-16 DATA GENERATORS/MULTIPLEXERS WITH 3-STATE OUTPUTS S DAS137A-DECEM BER 1 9 8 3 - REVISED DECEMBER 1994 4-Line to 1-Line Multiplexers That Can Select 1-of-16 Data Inputs Applications: Boolean Function Generator Parallel-to-Serial Converter

Contextual Info: TEXAS INSTR LOGIC 2 aU l 7 a 3 DOfiLtiltj (a SE D SN54HC194, SN74HC194 4-BIT BIDIRECTIONAL UNIVERSAL SHIFT REGISTERS 02684, DECEMBER 1982-REVISED JUNE 1989 SN54HC194 , . . J PACKAGE S N 7 4 H C 1 9 4 . . N PACKAGE (TOP VIEW) Four Operating Modes: Synchronous Parallel Load

ACT240

Abstract: SN54ACT240 SN74ACT240
Contextual Info: SN54ACT240, SN74ACT240 OCTAL BUFFERS/DRIVERS WITH 3-STATE OUTPUTS SCAS515A - JUNE 1995 - REVISED SEPTEMBER 1995 Inputs Are TTL Compatible SN54ACT240 . . . J OR W PACKAGE SN74ACT240 . . . DB, DW, N, OR PW PACKAGE TOP VIEW E P IC (Enhanced-Performance Implanted

D102H71

Abstract: SN74ALVCH16823
Contextual Info: SN74ALVCH16823 18-BIT BUS-INTERFACE FLIP-FLOP WITH 3-STATE OUTPUTS S C E S 0 3 8 -J U L Y 1995 DGG OR DL PACKAGE TOP VIEW • Member of the Texas Instruments Wldebus Family • EPIC™ (Enhanced-Performance Implanted CMOS) Submicron Process • ESD Protection Exceeds 2000 V Per

SN74ACT7811

Abstract: SN74ACT7881 SN74ACT7882 SN74ACT7884 1754C
Contextual Info: SN74ACT7811 1024 x 18 CLOCKED FIRST-IN, FIRST-OUT MEMORY WITH 3-STATE OUTPUTS SCAS151A - JANUARY 1991 - R E V IS E D FEBRUARY 1992 • Input-Ready, Output-Ready, and Half-Full Flags • Cascadable In Word Width and/or Word Depth Member of the Texas Instruments

Contextual Info: 74ACT11240 OCTAL BUFFER/LINE DRIVER WITH 3-STATE OUTPUTS SCAS21OA - MAY 1987 - R EVISED APRIL 1996 Inputs Are TTL-Voltage Compatible DB, DW, OR NT PACKAGE TO P VIEW Flow-Through Architecture Optimizes PCB Layout 1Y1 [ , 1Y2 [ 2 1Y3 [ 3 Center-Pin V cc and G N ° Configurations

SN54BCT8240A

Abstract: SN74BCT8240A
Contextual Info: SN54BCT8240A, SN74BCT8240A SCAN TEST DEVICES WITH OCTAL BUFFERS SCBS067C - FEBRUARY 1990 - REVISED APRIL 1994 Members of the Texas Instruments SCOPE Family of Testability Products Octal Test-Integrated Circuits Functionally Equivalent to SN54/74F240 and SN54/74BCT240 in the Normal­

Contextual Info: 54ACT11021, 74ACT11021 DUAL 4-INPUT POSITIVE-AND GATES SCAS012B - D2957, JULY 1978 - REVISED APRIL 1993 • * Inputs Are TTL-Voltage Compatible I I * Flow-Through Architecture Optimizes PCB Layout I | * Center-Pin V qc and GND Configurations Minimize High-Speed Switching Noise

Contextual Info: 74ACT11646 OCTAL BUS TRANSCEIVER AND REGISTER WITH 3-STATE OUTPUTS SCAS061A - 02957. JULY 1987 - REVISED APRIL 1993 DW P A C K A G E TOP VIEW • Independent Registers for A and B Bu ses • Multiplexed Real-Time and Stored Data • Flow-Through Architecture Optimizes