EX256-TQ100
Abstract: No abstract text available
Text: Revision 10 eX Family FPGAs Leading Edge Performance • 240 MHz System Performance • 350 MHz Internal Performance • 3.9 ns Clock-to-Out Pad-to-Pad Specifications • 3,000 to 12,000 Available System Gates • Maximum 512 Flip-Flops (Using CC Macros)
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UA 796
Abstract: 40B5 42B2 RT54SX-S TQFP-64 PACKAGE thermal resistance bst web guiding uA796 UA 795
Text: Revision 9 eX Family FPGAs FuseLock Leading Edge Performance • 240 MHz System Performance • 350 MHz Internal Performance • 3.9 ns Clock-to-Out Pad-to-Pad Specifications • 3,000 to 12,000 Available System Gates • Maximum 512 Flip-Flops (Using CC Macros)
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RTSX32
Abstract: RT54SX32-CQ208 trd24 RTSX16 54SX A54SX16 A54SX32 RT54SX RT54SX72S Actel PQFP208
Text: v2.1 SX Family FPGAs RadTolerant and HiRel Features High Density Devices • • • RadTolerant SX Family • • • • • • Tested Total Ionizing Dose TID Survivability Level Radiation Performance to 100 Krads (Si) (ICC Standby Parametric) Devices Available from Tested Pedigreed Lots
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208-Pin CQFP
Abstract: Actel PQFP208 RTSX32
Text: v2.1 SX Family FPGAs RadTolerant and HiRel Features High Density Devices • • • RadTolerant SX Family • • • • • • Tested Total Ionizing Dose TID Survivability Level Radiation Performance to 100 Krads (Si) (ICC Standby Parametric) Devices Available from Tested Pedigreed Lots
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40B5
Abstract: 42B2 RT54SX-S TQ100
Text: v4.1 eX Family FPGAs FuseLock Leading Edge Performance • • • • • 240 MHz System Performance 350 MHz Internal Performance 3.9 ns Clock-to-Out Pad-to-Pad • • • Specifications • • • • • 3,000 to 12,000 Available System Gates Maximum 512 Flip-Flops (Using CC Macros)
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Silicon Sculptor II
Abstract: 40B5 42B2 RT54SX-S TQ100 180-pin
Text: v4.3 eX Family FPGAs FuseLock Leading Edge Performance • • • • • 240 MHz System Performance 350 MHz Internal Performance 3.9 ns Clock-to-Out Pad-to-Pad • • • Specifications • • • • • 3,000 to 12,000 Available System Gates Maximum 512 Flip-Flops (Using CC Macros)
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silicon sculptor
Abstract: 40B5 Silicon Sculptor II 42B2 RT54SX-S TQ100 180-pin actel EX128 TQ100 EX256-TQ100
Text: v4.2 eX Family FPGAs FuseLock Leading Edge Performance • • • • • 240 MHz System Performance 350 MHz Internal Performance 3.9 ns Clock-to-Out Pad-to-Pad • • • Specifications • • • • • 3,000 to 12,000 Available System Gates Maximum 512 Flip-Flops (Using CC Macros)
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Untitled
Abstract: No abstract text available
Text: v4.2 eX Family FPGAs FuseLock Leading Edge Performance • • • • • 240 MHz System Performance 350 MHz Internal Performance 3.9 ns Clock-to-Out Pad-to-Pad • • • Specifications • • • • • 3,000 to 12,000 Available System Gates Maximum 512 Flip-Flops (Using CC Macros)
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Untitled
Abstract: No abstract text available
Text: v2 . 1 RTSX-S RadTolerant FPGAs Designed for Space • • • • • SEU-Hardened Registers Eliminate the Need to Implement Triple-Module Redundancy TMR – Immune to Single-Event Upsets (SEU) to LETth > 40 MeV-cm2/mg, – SEU Rate < 10–10 Upset/Bit-Day in Worst-Case
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TM1019
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RT54SX72SCQ208
Abstract: Actel a54sx72a tid RT54SX72S matsua fuse resistor PQFP die size actel 1020 datasheet ACTEL CCGA 624 mechanical antifuse A54SX72A CC256
Text: v2 . 2 RTSX-S RadTolerant FPGAs Designed for Space • • • • • SEU-Hardened Registers Eliminate the Need to Implement Triple-Module Redundancy TMR – Immune to Single-Event Upsets (SEU) to LETth > 40 MeV-cm2/mg, – SEU Rate < 10–10 Upset/Bit-Day in Worst-Case
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TM1019
RT54SX72SCQ208
Actel a54sx72a tid
RT54SX72S
matsua fuse resistor
PQFP die size
actel 1020 datasheet
ACTEL CCGA 624 mechanical
antifuse
A54SX72A
CC256
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ACTEL CCGA 624 mechanical
Abstract: No abstract text available
Text: v2 . 0 RTSX-S RadTolerant FPGAs Designed for Space • • • • • SEU-Hardened Registers Eliminate the Need to Implement Triple-Module Redundancy TMR – Immune to Single-Event Upsets (SEU) to LETth > 40 MeV-cm2/mg, – SEU Rate < 10–10 Upset/Bit-Day in Worst-Case
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TM1019
ACTEL CCGA 624 mechanical
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ACTEL CCGA 624 mechanical
Abstract: 208-Pin CQFP Actel a54sx72a tid CCGA -CG 472
Text: v2 . 2 RTSX-S RadTolerant FPGAs Designed for Space • • • • • SEU-Hardened Registers Eliminate the Need to Implement Triple-Module Redundancy TMR – Immune to Single-Event Upsets (SEU) to LETth > 40 MeV-cm2/mg, – SEU Rate < 10–10 Upset/Bit-Day in Worst-Case
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TM1019
ACTEL CCGA 624 mechanical
208-Pin CQFP
Actel a54sx72a tid
CCGA -CG 472
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Silicon Sculptor II
Abstract: No abstract text available
Text: v4.0 eX Family FPGAs FuseLock Le a di n g E d ge P er f o r m a n ce • 240 MHz System Performance • 350 MHz Internal Performance • 3.9 ns Clock-to-Out Pad-to-Pad • No Power-Up/Down Sequence Required for Supply Voltages • Configurable Weak-Resistor Pull-Up or Pull-Down for
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vq80
Abstract: A40MX02 one time
Text: Revision 3 40MX and 42MX Automotive FPGA Families Features High Capacity Ease of Integration • Single-Chip Applications ASIC Alternative for Automotive • Up to 100% Resource Utilization and 100% Pin Locking • 3,000 to 54,000 System Gates • Deterministic, User-Controllable Timing
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RTSX32su
Abstract: RTSX32SU CQ84 RTSX72SU
Text: v2.0 RTSX-SU RadTolerant FPGAs UMC u e Designed for Space • • • • • SEU-Hardened Registers Eliminate the Need to Implement Triple-Module Redundancy (TMR) – Immune to Single-Event Upsets (SEU) to LETth > 40 MeV-cm2/mg, – SEU Rate < 10–10 Upset/Bit-Day in Worst-Case
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TM1019
RTSX32su
RTSX32SU CQ84
RTSX72SU
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RTSX32SU
Abstract: RTSX32 PQFP die size C5249 bst r16 166 P790 actel 1020 datasheet A54SX72A CC256 CQ208
Text: Advanced v0.3 RTSX-SU RadTolerant FPGAs UMC u e Designed for Space • • • • • SEU-Hardened Registers Eliminate the Need to Implement Triple-Module Redundancy (TMR) – Immune to Single-Event Upsets (SEU) to LETth > 40 MeV-cm2/mg, – SEU Rate < 10–10 Upset/Bit-Day in Worst-Case
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TM1019
RTSX32SU
RTSX32
PQFP die size
C5249
bst r16 166
P790
actel 1020 datasheet
A54SX72A
CC256
CQ208
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RTSX72
Abstract: RTSX72SU A54SX72A TID "tristate buffer" A54SX32S-PQ208 RT54SXproto
Text: Advanced v0.2 RTSX-SU RadTolerant FPGAs UMC u e Designed for Space • • • • • SEU-Hardened Registers Eliminate the Need to Implement Triple-Module Redundancy (TMR) – Immune to Single-Event Upsets (SEU) to LETth > 40 MeV-cm2/mg, – SEU Rate < 10–10 Upset/Bit-Day in Worst-Case
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RTSX72
RTSX72SU
A54SX72A TID
"tristate buffer"
A54SX32S-PQ208
RT54SXproto
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SU 177
Abstract: RTSX32SU A54SX72* radiation Actel a54sx72a tid antifuse A54SX72A CC256 CG624 CQ208 CQ256
Text: Advanced v0.3 RTSX-SU RadTolerant FPGAs UMC u e Designed for Space • • • • • SEU-Hardened Registers Eliminate the Need to Implement Triple-Module Redundancy (TMR) – Immune to Single-Event Upsets (SEU) to LETth > 40 MeV-cm2/mg, – SEU Rate < 10–10 Upset/Bit-Day in Worst-Case
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TM1019
SU 177
RTSX32SU
A54SX72* radiation
Actel a54sx72a tid
antifuse
A54SX72A
CC256
CG624
CQ208
CQ256
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RTSX32su
Abstract: Actel a54sx72a tid Silicon Sculptor II
Text: v2.2 RTSX-SU RadTolerant FPGAs UMC u e Designed for Space • • • • • SEU-Hardened Registers Eliminate the Need to Implement Triple-Module Redundancy (TMR) – Immune to Single-Event Upsets (SEU) to LETth > 40 MeV-cm2/mg, – SEU Rate < 10–10 Upset/Bit-Day in Worst-Case
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TM1019
RTSX32su
Actel a54sx72a tid
Silicon Sculptor II
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RTSX72
Abstract: No abstract text available
Text: v2.2 RTSX-SU RadTolerant FPGAs UMC u e Designed for Space • • • • • SEU-Hardened Registers Eliminate the Need to Implement Triple-Module Redundancy (TMR) – Immune to Single-Event Upsets (SEU) to LETth > 40 MeV-cm2/mg, – SEU Rate < 10–10 Upset/Bit-Day in Worst-Case
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TM1019
RTSX72
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RTSX32SU CQ84
Abstract: Silicon Sculptor II RTSX32SU actel 1020
Text: v2.1 RTSX-SU RadTolerant FPGAs UMC u e Designed for Space • • • • • SEU-Hardened Registers Eliminate the Need to Implement Triple-Module Redundancy (TMR) – Immune to Single-Event Upsets (SEU) to LETth > 40 MeV-cm2/mg, – SEU Rate < 10–10 Upset/Bit-Day in Worst-Case
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TM1019
RTSX32SU CQ84
Silicon Sculptor II
RTSX32SU
actel 1020
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RTSX32SU
Abstract: RTSX32SU CQ84 Actel a54sx72a tid RTSX72SU RTSX-SU actel 1020 Silicon Sculptor II actel 1020 datasheet RT54SX E11213
Text: v2.2 RTSX-SU RadTolerant FPGAs UMC u e Designed for Space • • • • • SEU-Hardened Registers Eliminate the Need to Implement Triple-Module Redundancy (TMR) – Immune to Single-Event Upsets (SEU) to LETth > 40 MeV-cm2/mg, – SEU Rate < 10–10 Upset/Bit-Day in Worst-Case
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TM1019
RTSX32SU
RTSX32SU CQ84
Actel a54sx72a tid
RTSX72SU
RTSX-SU
actel 1020
Silicon Sculptor II
actel 1020 datasheet
RT54SX
E11213
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RTSX32SU
Abstract: RTSX32SU CQ84 rtsx72su RTSX32 RTSX-SU 1/RTSX32su CC256 PRB-1 actel 1020 datasheet CG624
Text: Revision 7 RTSX-SU RadTolerant FPGAs UMC FuseLock Designed for Space • • • • • SEU-Hardened Registers Eliminate the Need to Implement Triple-Module Redundancy (TMR) – Immune to Single-Event Upsets (SEU) to LETth > 40 MeV-cm2/mg, – SEU Rate < 10–10 Upset/Bit-Day in Worst-Case
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TM1019
MIL-ST00
RTSX32SU
RTSX32SU CQ84
rtsx72su
RTSX32
RTSX-SU
1/RTSX32su
CC256
PRB-1
actel 1020 datasheet
CG624
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RTSX32SU CQ84 PROTO
Abstract: CQ84 SOC 8A fuse smd RTSX32SU CQ84 rtsx72su RTSX32SU CG624 thermal expansion
Text: Revision 8 RTSX-SU Radiation-Tolerant FPGAs UMC Designed for Space • SEU-Hardened Registers Eliminate the Need to Implement Triple-Module Redundancy (TMR) – Immune to Single Event Upsets (SEU) to LETth > 40 MeVcm2/mg, – SEU Rate < 10–10 Upset/Bit-Day in Worst-Case
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TM1019
RTSX32SU CQ84 PROTO
CQ84
SOC 8A fuse smd
RTSX32SU CQ84
rtsx72su
RTSX32SU
CG624 thermal expansion
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