sync rs-485 SDLC
Abstract: No abstract text available
Text: Dual Channel High Speed Serial Interface Synch/Async RS-530/422/485 Operation SERIAL I/O IBM PC OMG-ACB-530 299 $ Basic Unit MADE IN USA Applications ߜ Users Requiring Protocols such as SDLC, HDLC, X.25, MONOSYNC, BISYNC, and ASYNC ߜ Fractional T1 Pipelines/Data Highways
|
Original
|
PDF
|
RS-530/422/485
OMG-ACB-530
OMG-ACB-530-II
D4-32
IEEE-488
95/98/Me/NT/2000
sync rs-485 SDLC
|
SC28L198
Abstract: SCN2681 SC28L194 SC26C92 SC28L92 SC68C562 SCC2691 SCC2692 SCC68692 SCN26562
Text: Philips Semiconductors UART/DUSCC selection guide ASYNCHRONOUS SYNCH OR ASYNCH SYSTEM NO = SIMPLE UART u1 CHANNEL SCC2691 CMOS SYNCHRONOUS YES SYNCHRONOUS BISYNC, HDLC u2 CHANNEL NO NO LOW POWER OR HIGH SPEED SCN2681 2 CHANNELS 28/40 NMOS 28/40 PIN SCN68681
|
Original
|
PDF
|
SCC2691
SCN2681
SCN68681
SCC2692
SCC68692
SCC26C562
SCN26562
SC68C562
SC28L92
SCN68562
SC28L198
SCN2681
SC28L194
SC26C92
SC28L92
SC68C562
SCC2691
SCC2692
SCC68692
SCN26562
|
Bi-phase-L Coding
Abstract: CRC16 D555 MPC821 manchester differential
Text: Communication Processor Module 16.14 SERIAL COMMUNICATION CONTROLLERS The following is a list of the SCCs’ important features: • Implements HDLC/SDLC, HDLC bus, asynchronous HDLC, BISYNC, synchronous start/stop, asynchronous start/stop UART , AppleTalk/LocalTalk, and totally
|
Original
|
PDF
|
10-Mbps
MPC821
Bi-phase-L Coding
CRC16
D555
manchester differential
|
stk 412 -770
Abstract: STK 412 770 CL-CD2401 stk 2261 STK 407 - 240 80X86 CL-CD2231 CL-CD2431 CRC16 CRC-16
Text: CL-CD2401 Data Book FEATURES • Four full-duplex multi-protocol channels, each running up to 134.4 kbits/sec. @ CLK = 35 MHz ■ Supports async, HDLC/SDLC (synchronous data link control; non-multidrop applications), bisync and X.21 on all channels ■ 32-bit address, 16-bit data, double-buffered DMA controller for each transmitter and receiver; two
|
Original
|
PDF
|
CL-CD2401
32-bit
16-bit
stk 412 -770
STK 412 770
CL-CD2401
stk 2261
STK 407 - 240
80X86
CL-CD2231
CL-CD2431
CRC16
CRC-16
|
DB15 dwg
Abstract: CRC-16 DB01 DB03 SCN2653
Text: Philips Semiconductors Product specification Multi-protocol communications controller MPCC DESCRIPTION SCN2652/SCN68652 FEATURES • DC to 2Mbps data rate • Bit-oriented protocols (BOP): SDLC, ADCCP, HDLC • Byte-control protocols (BCP): DDCMP, BISYNC (external CRC)
|
Original
|
PDF
|
SCN2652/SCN68652
SCN2652/68652
16-bit
SCN2652
SD00075
SCN2652/SCN2653
DB15 dwg
CRC-16
DB01
DB03
SCN2653
|
sdlc schematic
Abstract: IN SDLC PROTOCOL SDLC 000D 001C WR10 Z80185 WR1 marking code
Text: USER’S MANUAL CHAPTER 12 ESCC 12.1 INTRODUCTION This element of the Z80185 allows serial communications in a variety of modes, including asynchronous start-stop , character-oriented synchronous modes like IBM's Bisync, and bit-oriented synchronous modes like IBM's SDLC,
|
Original
|
PDF
|
Z80185
Z801x5
UM971800200
sdlc schematic
IN SDLC PROTOCOL
SDLC
000D
001C
WR10
WR1 marking code
|
CL-CD2401
Abstract: 80X86 CD2401 CL-CD2231 CL-CD2431 CRC-16 STK 432 P585A manchester
Text: CL-CD2401 Data Book FEATURES • Four full-duplex multi-protocol channels, each running up to 134.4 kbits/sec. @ CLK = 35 MHz ■ Supports async, HDLC/SDLC (synchronous data link control; non-multidrop applications), bisync and X.21 on all channels ■ 32-bit address, 16-bit data, double-buffered DMA controller for each transmitter and receiver; two
|
Original
|
PDF
|
CL-CD2401
32-bit
16-bit
CL-CD2401
80X86
CD2401
CL-CD2231
CL-CD2431
CRC-16
STK 432
P585A
manchester
|
SDLC synchronous signals
Abstract: 82530 TDA echo
Text: Features • • • • • • • • • • Serial Communication Controller Two Independent Full-duplex Channels Asynchronous and Synchronous Modes MONOSYNC, BISYNC and SDLC Loop Mode Supported SDLC Loop Mode Supported NRZ, NRZI and FM Encoding/Decoding
|
Original
|
PDF
|
|
Untitled
Abstract: No abstract text available
Text: CIRRUS LOGIC FEATURES Data Sheet Four-Channel, Multi-Protocol Communications Controller GeneraI • Four full-duplex channels ■ All channels support async, bisync, HDLC/ SDLC, and X.21 programmable sync protocols ■ Bit rates to 64 kbit transmit and receive NRZ,
|
OCR Scan
|
PDF
|
|
Untitled
Abstract: No abstract text available
Text: SC11091/SC11095 2400 bps Universal Modem Advanced Controller SIERRA SEMICONDUCTOR □ Supports SD L C , H D L C , Bisync, M onosync & A sync protocols in softw are □ Reverse com patible w ith S C I 1011,21, 61 □ D irect interface to S C I 1006, SC11024, SC11026, SC11044,
|
OCR Scan
|
PDF
|
SC11091/SC11095
SC11024,
SC11026,
SC11044,
SC11091CV
SC11095CV
16x16
80-PIN
|
8089 intel microprocessor Architecture Diagram
Abstract: intel d 8274 8085 microprocessor serial communication 8086 8257 DMA controller 8085 interrupt intel 8274 WR1 marking code intel 8085 clock 8089 microprocessor architecture MCS-48
Text: in te i 8274 MULTI-PROTOCOL SERIAL CONTROLLER MPSC Byte Synchronous: — Character Synchronization, Int. or Ext. — One or Two Sync Characters — Automatic CRC Generation and Checking (CRC-16) — IBM Bisync Compatible Asynchronous, Byte Synchronous and
|
OCR Scan
|
PDF
|
CRC-16)
8089 intel microprocessor Architecture Diagram
intel d 8274
8085 microprocessor serial communication
8086 8257 DMA controller
8085 interrupt
intel 8274
WR1 marking code
intel 8085 clock
8089 microprocessor architecture
MCS-48
|
Untitled
Abstract: No abstract text available
Text: P r e l im in a r y P r o d u c t S p e c if ic a t io n 7,l i n e Z16C30 CMOS USC MAY 1989 U n iv e r s a l S e r ia l C o n t r o l l e r FEATURES • 32 byte data FIFO’s for each receiver and transmitter. ■ Transparent Bisync mode with EBCDIC or ASCII
|
OCR Scan
|
PDF
|
Z16C30
|
Untitled
Abstract: No abstract text available
Text: P r o d u c t S p e c if ic a t io n < £ > 2 iL 0 5 Z16C30 CMOS USC UNIVERSAL S e r ia l co ntro ller FEATURES • Transparent Bisync M ode with EBCDIC or ASCII C h a ra c te r C o d e ; A u to m a tic C R C H a n d lin g ; Program mable Idle Line Condition; O ptional Preamble
|
OCR Scan
|
PDF
|
Z16C30
16-Bit
32-BitÃ
Z16C30
68-Pin
Z16C3010VSC
16C30
Z16C30,
|
intel d 8274
Abstract: intel 8274 8086 8257 DMA controller mpsc 07 Intel 8237 dma controller block diagram 8089 intel microprocessor Architecture Diagram 8085 microprocessor based communication mpsc2 instruction set of 8086 microprocessor 8085 microprocessor serial communication
Text: in te i 8274 MULTI-PROTOCOL SERIAL CONTROLLER MPSC Byte Synchronous: — Character Synchronization, Int. or Ext. — One or Two Sync Characters — Automatic CRC Generation and Checking (CRC-16) — IBM Bisync Compatible Bit Synchronous: — SDLC/HDLC Flag Generation and
|
OCR Scan
|
PDF
|
CRC-16)
intel d 8274
intel 8274
8086 8257 DMA controller
mpsc 07
Intel 8237 dma controller block diagram
8089 intel microprocessor Architecture Diagram
8085 microprocessor based communication
mpsc2
instruction set of 8086 microprocessor
8085 microprocessor serial communication
|
|
|
Untitled
Abstract: No abstract text available
Text: P r o d u c t S p e c if ic a t io n Z16C30 CMOS USC UNIVERSAL SERIAL CONTROLLER FEATURES • Transparent Bisync mode with EBCDIC or ASCII ch a ra c te r cod e; au to m a tic CRC handling; programmable idle line condition; optional preamble transmission; automatic recognition of DLE, SYN, SOH,
|
OCR Scan
|
PDF
|
Z16C30
16-bit)
32-bit
|
SC11091CV
Abstract: 8096 instruction set SC11054 mc9346n intel 8096 instruction set SC11091 SC11091CQ
Text: SC11091/SC11095 2400 bps Universal Modem Advanced Controller SIERRA SEMICONDUCTOR □ Supports M NP2-5 and CCITT V.42bis SC11091 , CCITT V.42 (SCI 1091 /SC I 1095) □ Supports SDLC, HDLC, Bisync, M onosync & Async protocols in software Internal Serial Synchronous
|
OCR Scan
|
PDF
|
SC11091/SC11095
68-PIN
42bis
SC11091)
16x16
SCU011,
SC11024,
SC11044,
SC11054
SC11091CV
8096 instruction set
mc9346n
intel 8096 instruction set
SC11091
SC11091CQ
|
BS421
Abstract: Unitrode Semiconductor transistor t220
Text: n i C R O S E M I CO RP/ lilATERTOUN 5ÜE D • T B H T T b B G G l E l S h STD « U N I T BISYN SYNCHRONOUS RECTIFIER U BS421 For Low-Voltage < 5.0V Loads FEATURES • Very Low On Resistance, Typically T- ? s-~ / 9 DESCRIPTION The BISYN is a bipolar junction transistor specifically designed to perform the rectifying
|
OCR Scan
|
PDF
|
BS421
BS421
Unitrode Semiconductor
transistor t220
|
0884A
Abstract: No abstract text available
Text: Features * * * * * * * * * * Serial Communication Controller Two Independent Full-duplex Channels Asynchronous and Synchronous Modes MONOSYNC, BISYNC and SDLC Loop Mode Supported SDLC Loop Mode Supported NRZ, NRZI and FM Encoding/Decoding Digital PLL for Each Channel
|
OCR Scan
|
PDF
|
|
SC11091
Abstract: NYP196-18 mc9346 H 74LS04 8096 instruction 74HCT00A SC11054 sc11011
Text: *C> SC11091 2400 bps Universal Modem Advanced Controller s ie r r a se m ic o n d u c t o r 68-PIN PLCC PACKAGE can □ S upports V.42bis & M N PW □ S u pports SDLC, HDLC,Bisync, M onosync & A sync.protocols in softw are □ Internal Serial S ynchronous
|
OCR Scan
|
PDF
|
42bis
64KROM
16X16
SC11046
SC11054,
SK9698
SC1100g
J5P312A8-29
HC49/U
SRX3860
SC11091
NYP196-18
mc9346
H 74LS04
8096 instruction
74HCT00A
SC11054
sc11011
|
GT1 X02
Abstract: bdv21 CD2401 80X86 CL-CD2231 CL-CD2401 CL-CD2431 GT11 V7021 STK 412 240
Text: CL-CD2401 DataBook 'CIRRUS LOGIC " FEATURES • Four full-duplex multi-protocol channels, each running up to 134.4 kbits/sec. @ C L K = 35 MHz ■ Supports async, HDLC/SDLC (synchronous data link control; non-multidrop applications), bisync and X.21 on all channels
|
OCR Scan
|
PDF
|
CL-CD2401
32-bit
16-bit
GT1 X02
bdv21
CD2401
80X86
CL-CD2231
CL-CD2401
CL-CD2431
GT11
V7021
STK 412 240
|
ubs421
Abstract: bisyn UBS-421
Text: BISYN SYNCHRONOUS RECTIFIER UBS421 For Low-Voltage < 5.0V Loads FEATURES • Very Low On Resistance, Typically 1 4 m fi • H igh Reverse B lockin g V e c s - 40V • Can be PWM C ontrolled to Provide Regulated Voltage to Load DESCRIPTION The BISYN is a bipolar ju n c tio n tra n sisto r sp ecifica lly designed to perform the rectifying
|
OCR Scan
|
PDF
|
UBS421
ubs421
bisyn
UBS-421
|
UBS430
Abstract: transistor s43 12ALC ic se 617
Text: BISYN" SYNCHRONOUS RECTIFIER UBS430 For Low-Voltage <5.0V Loads FEATURES • Very Low O n R esistance — Typically 7 m illiohm s • H igh Reverse B lo cking Voltage — V e c s = 40V • Can be PW M Controlled to Provide Regulated Voltage to Load • Low Tem perature Coefficient of On
|
OCR Scan
|
PDF
|
UBS430
UBS430
transistor s43
12ALC
ic se 617
|
74007
Abstract: 74009 7404D 7400D
Text: P hilips Sem iconductors Data C om m unications Products A pplication note User notes for the SCN68/26562 NDUSCC and SC68/26C562 (CDUSCC) Revised by: A. Kazmi BISYNC Protocol Questions and Answers - Program Tx to underrun with SYN s (TPR[7:6] = 11) This is a list of some questions and answers for the
|
OCR Scan
|
PDF
|
SCN68/26562
SC68/26C562
--210K
74007
74009
7404D
7400D
|
TMPZ84
Abstract: TMPZ84C40
Text: TO SH IBA TMPZ84C40A/41A/42A/43A/44A TMPZ84C40AP-6 / 41AP-6 / 42AP-6 / 43AF-6 / 44AT-6 TMPZ84C40AM-6 /41AM-6 / 42AM-6 TMPZ84C40AP-8 / 41AP-8 / 42AP-8 TLCS-Z80 SIO: SERIAL INPUT/OUTPUT CONTROLLER 1. GENERAL DESCRIPTION AND FEATURES The TMPZ84C40A SIO/O , TMPZ84C41A (SIO/1), TMPZ84C42A (SIO/2),
|
OCR Scan
|
PDF
|
TMPZ84C40A/41A/42A/43A/44A
TMPZ84C40AP-6
41AP-6
42AP-6
43AF-6
44AT-6
TMPZ84C40AM-6
/41AM-6
42AM-6
TMPZ84C40AP-8
TMPZ84
TMPZ84C40
|