GT1 X02
Abstract: CD2401 80X86 CD2231 CD2431 CD2481 CL-CD2401
Text: CD2401 Multi-Protocol Communications Controller Datasheet The CD2401 is a four-channel synchronous/asynchronous communications controller, specifically designed to reduce host-system processing overhead and increase efficiency in a wide variety of communications applications. The CD2401 is available in a 100-pin MQFP
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CD2401
CD2401
100-pin
GT1 X02
80X86
CD2231
CD2431
CD2481
CL-CD2401
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stk 412 -770
Abstract: STK 412 770 CL-CD2401 stk 2261 STK 407 - 240 80X86 CL-CD2231 CL-CD2431 CRC16 CRC-16
Text: CL-CD2401 Data Book FEATURES • Four full-duplex multi-protocol channels, each running up to 134.4 kbits/sec. @ CLK = 35 MHz ■ Supports async, HDLC/SDLC (synchronous data link control; non-multidrop applications), bisync and X.21 on all channels ■ 32-bit address, 16-bit data, double-buffered DMA controller for each transmitter and receiver; two
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CL-CD2401
32-bit
16-bit
stk 412 -770
STK 412 770
CL-CD2401
stk 2261
STK 407 - 240
80X86
CL-CD2231
CL-CD2431
CRC16
CRC-16
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CL-CD2401
Abstract: 80X86 CD2401 CL-CD2231 CL-CD2431 CRC-16 STK 432 P585A manchester
Text: CL-CD2401 Data Book FEATURES • Four full-duplex multi-protocol channels, each running up to 134.4 kbits/sec. @ CLK = 35 MHz ■ Supports async, HDLC/SDLC (synchronous data link control; non-multidrop applications), bisync and X.21 on all channels ■ 32-bit address, 16-bit data, double-buffered DMA controller for each transmitter and receiver; two
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CL-CD2401
32-bit
16-bit
CL-CD2401
80X86
CD2401
CL-CD2231
CL-CD2431
CRC-16
STK 432
P585A
manchester
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94v0 decoder
Abstract: 53c710 94v-0 dynamic RAM mv177 MK48T58 i82596CA MVME177P-64SE MVME177P-67SE MC68060 CD2401
Text: MVME177P Single-Board Computer ♦ 50 or 60 MHz MC68060 32-bit microprocessor with 8KB of cache, MMU, and FPU ♦ Full 32-bit master/slave VMEbus interface ♦ High-performance DMA supports VMEbus D64 and local bus memory burst cycles ♦ 16, 32, 64 or 128MB configurable
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MVME177P
MC68060
32-bit
32-bit
128MB
128KB
EIA-232-D)
MV177-D7
94v0 decoder
53c710
94v-0 dynamic RAM
mv177
MK48T58
i82596CA
MVME177P-64SE
MVME177P-67SE
CD2401
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petra
Abstract: MK48T58 94v0 decoder MVME712M i82596CA VRTX32 MVME177 i82596 mv177 VME COnnector
Text: Datasheet M V M E 17 7 PA S in g l e -B o a r d Computer Combination of superscalar microprocessor and world-class quality VME products The company that pioneered the VMEbus single-board computer has added new dimensions in performance and functionality. Motorola’s third-generation single-board
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MVME177PA,
MC68060
MVME177PA
M68000
MV177-D10
petra
MK48T58
94v0 decoder
MVME712M
i82596CA
VRTX32
MVME177
i82596
mv177
VME COnnector
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mvme167
Abstract: MK48T08 94v0 decoder MC68040-25 MVME946 68-1X7DS MVME-167 MVME167-033 MV167-D2 mvme167-034
Text: M OT OR OL A CO MP UT ER G RO UP B o ar d L ev el P r o d u ct s M V M E 167 SI N G L E BO A RD C O M P U T E R A d va n t a g e s M o t o r o l a ’ s M V M E 1 6 7 s i n g l e b o a r d c o m p u te r r e p r e s e n ts t h e p i n n a c l e o f f u n c t i o n a l i ty , fl e x i b i l i t y , a n d p e r fo r m a n c e i n a CI S C b a s e d s y s te m . B a s e d o n th e m o s t p o w e r fu l CI S C m i c r o p r o c e s s o r
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CD2200
Abstract: 225401-3
Text: HIGH POWER 1000 WATT BIDIRECTIONAL COUPLERS FREQ. GHz MODEL NUMBER FREQ. COUPLING FLATNESS (dB) (±dB) INSERTION LOSS DIRECTIVITY (dB, Max.) (dB, Typ.) VSWR POWER (Max.) (Watts, Max.) PRI. SEC. AVG. AVG. LINE LINE FORWARD REVERSE PEAK (kW) OUTLINE 0.02–0.1
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CD2-200-101-30NK
CD2-200-101-40NK
CD2-101-501-30NK
CD2-101-501-40NK
CD2-225-401-30NK
CD2-225-401-40NK
CD2-401-102-30NK
CD2-401-102-40NK
CD2-801-162-30NK
CD2-801-162-40NK
CD2200
225401-3
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Untitled
Abstract: No abstract text available
Text: CL-CD2400/CD2401 M ulti-Protocol Com m unications Controller ’CIRRUS LOGIC 8. PACKAGE SPECIFICATIONS 8.1 84-Pin PLCC Plastic-Leaded Chip Carrier Package Data D 0.042 0.048 D1 rn n n E1 : : : c CL-CD2400 84-Pin PLCC U U LT 0.026 0.032 0.026 0.032 DIMENSION
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CL-CD2400/CD2401
84-Pin
CL-CD2400
100-Pin
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Multi-CL-CD2400
Abstract: No abstract text available
Text: CL-CD2400/CD2401 M u lti-P roto co l C om m unications C ontroller 3. FUNCTIONAL DESCRIPTION 3.1 H ost Interface 'CIRRUS LOGIC word transfers are supported in each of the Bus Slave and DMA Bus Master modes. Figure 3-1 and Figure 3-2 show the signals involved in these trans
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CL-CD2400/CD2401
CL-CD2400
RS-232-C
RS-232-C,
CL-CD2400
CL-CD2401
Multi-CL-CD2400
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RS7473
Abstract: fcs SDLC free stk ic
Text: 'CIRRUS LOGIC CL-CD2400/CD2401 D ata Book FEATURES Four-Channel, Multi-Protocol Communications Controller General • Four full-duplex channels ■ All channels support async, blsync, HDLC/ SDLC, and X.21 programmable sync protocols ■ Bit rates to 64 kbit transmit and receive, NRZ,
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CL-CD2400/CD2401
CL-CD2400
CL-CD2401
100-Pin
CL-CD2400I2401
CD2400
RS7473
fcs SDLC
free stk ic
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CD2401
Abstract: No abstract text available
Text: CL-CD2400/CD2401 M ulti-P rotocol Com m unications C ontroller "CIRRUS LOGIC Before beginning any new design with this device, please contact Cirrus Logic Inc. for the latest errata information. See the back cover of this document for sales office locations and
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CL-CD2400/CD2401
CL-CD2400/
CD2401
CD2401
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CD2401
Abstract: No abstract text available
Text: CL-CD2400/ CD2401 'CIRRUS LOGIC M u lti-P ro to c o l C o m m u n ic a tio n s C o n tro ller 9. ORDERING INFORMATION EXAMPLE CL - CD2400 - 10 PC - K CL - CD2401 - 1 0 Q C - K L T Cirrus Logic, Inc. Communications, Data —I Revision1 — Temperature Range:
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CL-CD2400/
CD2401
CD2400
CD2401
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Untitled
Abstract: No abstract text available
Text: CL-CD2400/CD2401 M u lti-P rotocol Com m unications C ontroller 4. PROTOCOL PROCESSING 4.1 H D LC P ro c e s s in g 4.1.1 FCS Frame C heck Sequence The FCS is a 16-bit standard computation used in HDLC, and defined in ISO 3309. This FCS algorithm is the same used with the synchronous HDLC oper
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CL-CD2400/CD2401
CL-CD2400
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Untitled
Abstract: No abstract text available
Text: CL-CD2400/CD2401 CIRRUS LOGIC 2. M u lti-P ro to c o l C o m m u n icatio n s C o n tro ller REGISTER TABLE Registers in the CL-CD2400/CD2401 are either Global or Per-Channel. The column ‘Address mode’ in the memory map in the following tables defines this attribute for each register. Only one set of Global
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CL-CD2400/CD2401
CL-CD2400/CD2401
2400own
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CD2401
Abstract: No abstract text available
Text: „_ _ CIRRUS LOGIC 6. CL-CD2400/CD2401 M ulti-Protocol Com m unications Controller - DETAILED REGISTER DESCRIPTIONS NOTE: In this section, when the CL-CD2400 is specified, it applies equally to the CL-CD2401.
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CL-CD2400/CD2401
CL-CD2400
CL-CD2401.
CL-CD2400/CD2401.
CD2401
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Untitled
Abstract: No abstract text available
Text: "CIRRUS LOGIC CL-CD2400/CD2401 M ulti-Protocol Com m unications Controller CONVENTIONS Abbreviations Symbol Units of measure ”C degree Celsius HF microfarad US microsecond 1,000 nanoseconds Hz hertz (cycle per second) Kbit kbits/second Kbyte kbytes/second
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CL-CD2400/CD2401
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D2400
Abstract: CD2401 CL-CD2401
Text: CL-CD2400/ CD2401 M ulti-Protocol Com m unications Controller CIRRUS LOGIC PIN INFORMATION Pin Diagram — CL-CD2400 = •& l l i i i i / CTS' O H TXCOUT/DTR*[0] C r t s *[o] r CTS‘ [1 ]C TXCOUT/DTR*[1 ] C RTS* [1 C GND C CTS‘ [2] L TXCOUT/DTR*[2] C RTS'[2) □
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CL-CD2400/
CD2401
CL-CD2400
/DJ8-15]
D2400
CL-CD2401
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Untitled
Abstract: No abstract text available
Text: CL-CD2400/CD2401 M ulti-Protocol Com m unications Controller 5. CIRRUS LOGIC PROGRAMMING EXAMPLES This section provides some examples of CL-CD2400 programming. Included are examples of Global and Per-Channel initialization, and two interrupt service routines. The code was written in Borland Turbo C+.
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CL-CD2400/CD2401
CL-CD2400
CL-CD2400
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GT1 X02
Abstract: bdv21 CD2401 80X86 CL-CD2231 CL-CD2401 CL-CD2431 GT11 V7021 STK 412 240
Text: CL-CD2401 DataBook 'CIRRUS LOGIC " FEATURES • Four full-duplex multi-protocol channels, each running up to 134.4 kbits/sec. @ C L K = 35 MHz ■ Supports async, HDLC/SDLC (synchronous data link control; non-multidrop applications), bisync and X.21 on all channels
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CL-CD2401
32-bit
16-bit
GT1 X02
bdv21
CD2401
80X86
CL-CD2231
CL-CD2401
CL-CD2431
GT11
V7021
STK 412 240
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CD2400
Abstract: w97-14 CL-CD2400 CL-CD2401 M77A stk 433 060 2262 remote control car t4148
Text: CL-CD2400/CD2401 rCfRRL/S LOGIC Data Book FEATURES Four-Channel, Multi-Protocol Communications Controller General • Four full-duplex channels ■ All channels support async, blsync, HDLC/ SDLC, and X.21 programmable sync protocols OVERVIEW ■ Bit rates to 64 kbit transmit and receive, NRZ,
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CL-CD2400/CD2401
CL-CD2401
100-Pin
CL-CD2400/2401
CD2400
10QC-I
w97-14
CL-CD2400
CL-CD2401
M77A
stk 433 060
2262 remote control car
t4148
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CL-CD2400
Abstract: No abstract text available
Text: CL-CD2400/CD2401 D a ta B o o k 'CIRRUS LOGIC FEATURES • Four full-duplex multi-protocol channels, each running up to 128 kbits/second ■ Supports async, async-HDLC high-level data link control , and HDLC/SDLC (synchronous data link control) on all channels
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CL-CD2400/CD2401
32-bit
16-bit
CL-CD2400
CL-CD2401
four-channel-CD2401
CL-CD2431
84-pin
100-pin
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Untitled
Abstract: No abstract text available
Text: CL-CD2400/CD2401 M ulti-Protocol Com m unications Controller 'CIRRUS LOGIC INDEX A E abbreviations 6 absolute maximum ratings 127 AC electrical characteristics bus arbitration 128 DMA read 128 DMA write 128 host read/write 129 interrupt acknowledge 129 acronyms 7
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CL-CD2400/CD2401
32-bit
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RFC-1331
Abstract: 105GT-2 80X86 CL-CD2401 CL-CD2431 gt22a iso 3309
Text: CL-CD2430/CD2431 DataBook i "CIRRUS LOGIC FEATURES • Intelligent 4-Channel Local and WAN Communications Controller Four full-duplex multi-protocol channels, each running up to 128 kbits/second ■ Supports async, async-HDLC high-level data link control , and HDLC/SDLC (synchronous data link
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CL-CD2430/CD2431
32-bit
16-bit
RFC-1331
RFC-1331
105GT-2
80X86
CL-CD2401
CL-CD2431
gt22a
iso 3309
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stk 412 -410
Abstract: stk 412 -420 stk 432 070 MM5823 STK 412 240 CIR 2262 cir 2262 af stk 412 -230 hiab STk 412 120
Text: S lB b b B R DDOtilS4 “i2 ñ m C I R wm. C L -C D 2 4 0 0 /C D 2401 •SK-H CIRRUS LOGIC Data Book FEATURES Four-Channel, Multi-Protocol Communications Controller General • Four full-duplex channels ■ All channels support async, blsync, HDLC/ SDLC, and X.21 programmable sync protocols
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000bl54
CL-CD2400/
CD2401
CL-CD2401
100-Pin
CL-CD2400/2401
CL-CD2400
10QC-I
stk 412 -410
stk 412 -420
stk 432 070
MM5823
STK 412 240
CIR 2262
cir 2262 af
stk 412 -230
hiab
STk 412 120
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