AS7C33512NTD18A Search Results

V17H

Contextual Info: February 2002 AS7C33512NTD16A AS7C33512NTD18A 3.3V 512K x 16/18 65$0 ZLWK 17'TM Features • • • • • • • • • • • • • • • • • Organization: 524,288 words × 16 or 18 bits NTD 1 architecture for efficient bus operation Fast clock speeds to 166 MHz in LVTTL/LVCMOS

AS7C33256PFD32A

Abstract: AS7C33256PFS32A AS7C33256PFS36A AS7C33512NTD18A AS7C33512PFD18A AS7C33512PFS18A
Contextual Info: November 2004 AS7C33512NTD18A 3.3V 512K x 18 Pipelined burst Synchronous SRAM with NTDTM Features • Byte write enables • Clock enable for operation hold • Multiple chip enables for easy expansion • 3.3V core power supply • 2.5V or 3.3V I/O operation with separate VDDQ

Contextual Info: December 2001 Preliminary Information AS7C33512NTD16A AS7C33512NTD18A 3.3V 512K x 16/18 65$0 ZLWK 17'TM* Features • • • • • • • • Organization: 524,288 words × 16 or 18 bits Fast clock speeds to 166 MHz in LVTTL/LVCMOS Fast clock to data access: 3.5/3.8/4.0/5.0 ns

Contextual Info: August 2002 Preliminary AS7C33512NTD18A 3.3V 512K x 18 65$0 ZLWK 17'TM Features • • • • • • • • • • • • • • • • • Organization: 524,288 words × 18 bits NTD 1 architecture for efficient bus operation Fast clock speeds to 166 MHz in LVTTL/LVCMOS

Contextual Info: February 2003 AS7C33512NTD16A AS7C33512NTD18A 3.3V 512K x 16/18 65$0 ZLWK 17'TM Features • • • • • • • • • • • • • • • • • Organization: 524,288 words × 16 or 18 bits NTD 1 architecture for efficient bus operation Fast clock speeds to 166 MHz in LVTTL/LVCMOS

AS7C33512NTD18A

Contextual Info: September 2001 Preliminary Information AS7C33512NTD16A AS7C33512NTD18A 3.3V 512K x 16/18 65$0 ZLWK 17'TM* Features • • • • • • • • Organization: 524,288 words × 16 or 18 bits Fast clock speeds to 166 MHz in LVTTL/LVCMOS Fast clock to data access: 3.5/3.8/4.0/5.0 ns

Contextual Info: December 2002 Preliminary AS7C33512NTD18A 3.3V 512K x 18 65$0 ZLWK 17'TM Features • • • • • • • • • • • • • • • • • Organization: 524,288 words × 18 bits NTD 1 architecture for efficient bus operation Fast clock speeds to 166 MHz in LVTTL/LVCMOS

Contextual Info: April 2004 AS7C33512NTD18A 3.3V 512K x 18 SRAM with NTDTM Features • • • • • • Organization: 524,288 words × 18 bits NTD 1 architecture for efficient bus operation Fast clock speeds to 166 MHz in LVTTL/LVCMOS Fast clock to data access: 3.0/3.5/3.8/4.0/5.0 ns

Contextual Info: August 2002 Preliminary AS7C33512NTD18A 3.3V 512K x 18 65$0 ZLWK 17'TM Features • • • • • • • • • • • • • • • • • Organization: 524,288 words × 18 bits NTD 1 architecture for efficient bus operation Fast clock speeds to 166 MHz in LVTTL/LVCMOS

Contextual Info: September 2001 Preliminary Information AS7C33512NTD16A AS7C33512NTD18A 3.3V 512K x 16/18 65$0 ZLWK 17'TM* Features • • • • • • • • Organization: 524,288 words × 16 or 18 bits Fast clock speeds to 166 MHz in LVTTL/LVCMOS Fast clock to data access: 3.5/3.8/4.0/5.0 ns

AS7C33512NTD18A

Contextual Info: March 2002 AS7C33512NTD16A AS7C33512NTD18A 3.3V 512K x 16/18 65$0 ZLWK 17'TM Features • • • • • • • • • • • • • • • • • Organization: 524,288 words × 16 or 18 bits NTD 1 architecture for efficient bus operation Fast clock speeds to 166 MHz in LVTTL/LVCMOS

Contextual Info: May 2003 AS7C33512NTD16A AS7C33512NTD18A 3.3V 512K x 16/18 65$0 ZLWK 17'TM • • • • • • • • • • Features • • • • • Organization: 524,288 words × 16 or 18 bits NTD 1 architecture for efficient bus operation Fast clock speeds to 166 MHz in LVTTL/LVCMOS

Contextual Info: June 2002 AS7C33512NTD16A AS7C33512NTD18A 3.3V 512K x 16/18 65$0 ZLWK 17'TM Features • • • • • • • • • • • • • • • • • Organization: 524,288 words × 16 or 18 bits NTD 1 architecture for efficient bus operation Fast clock speeds to 166 MHz in LVTTL/LVCMOS

Contextual Info: November 2000 Advance Information AS7C33512PFS16A AS7C33512PFS18A 3.3V 512K x 16/18 pipeline burst synchronous SRAM Features • Organization: 524,288 words × 16 or 18 bits • Fast clock speeds to 166 MHz in LVTTL/LVCMOS • Fast clock to data access: 3.5/3.8/4.0/5.0 ns

Contextual Info: August 2002 Preliminary AS7C33512PFS18A 3.3V 512K x 18 pipelined burst synchronous SRAM Features • Multiple chip enables for easy expansion • 3.3V core power supply • 2.5V or 3.3V I/O operation with separate VDDQ • 30 mW typical standby power in power down mode

Contextual Info: October 2001 Preliminary Information AS7C33512PFS16A AS7C33512PFS18A 3.3V 512K x 16/18 pipeline burst synchronous SRAM Features • Pentium®* compatible architecture and timing • Asynchronous output enable control • Economical 100-pin TQFP package

1H08S

Abstract: PI6C2405A-1HW ASM706CUA SOIC-6 microchip ADM809RAR ADM705AN MAX809SEUR T ASM5P2309-1H-16-S K7N163601B MAX810JEUR
Contextual Info: Supervisors Cross Reference Guide Alliance Maxim/Dallas IMP ASM1232LP DS1232LPS-2 IMP1232LP ASM1232LPCMA DS1232LP IMP1232LPCMA ASM1232LPEMA DS1232LP IMP1232LPEMA ASM1232LPN DS1232LP IMP1232LPN Analog Devices Micrel Microchip MIC1232N TC1232CPA - - - - - -

ADM809RAR

Abstract: AS7C256A hsbga 416 lcd cross reference IDT CYPRESS CROSS REFERENCE clocks DS1232* watch dog timer Product Selector Guide mbg* sot143 FS781 IDT74SSTV16857
Contextual Info: DISCLAIMER Alliance Semiconductor Corporation reserves the right to make changes to its products or specifications at any time, without notice, in order to improve design or performance and to supply the best possible product. Alliance Semiconductor does not assume any responsibility for use of any circuitry described other than the circuitry embodied

Contextual Info: June 2002 Preliminary AS7C33512PFS16A AS7C33512PFS18A 3.3V 512K x 16/18 pipeline burst synchronous SRAM Features • Multiple chip enables for easy expansion • 3.3V core power supply • 2.5V or 3.3V I/O operation with separate VDDQ • 30 mW typical standby power in power down mode

Contextual Info: September 2001 Preliminary Information AS7C33512PFD16A AS7C33512PFD18A 3.3V 512K x 16/18 pipeline burst synchronous SRAM Features • Pentium®* compatible architecture and timing • Asynchronous output enable control • Economical 100-pin TQFP package

Contextual Info: March 2002 AS7C33512PFD16A AS7C33512PFD18A 3.3V 512K x 16/18 pipeline burst synchronous SRAM Features • Asynchronous output enable control • Available in 100-pin TQFP and 119-pin BGA package • Byte write enables • Multiple chip enables for easy expansion

Contextual Info: April 2004 AS7C33256PFS32A AS7C33256PFS36A 3.3V 256K x 32/36 pipelined burst synchronous SRAM Features • • • • • • • • • • • • • • Organization: 262,144 words x 32 or 36 bits Fast clock speeds to 166 MHz in LVTTL/LVCMOS Fast clock to data access: 3.5/3.8/4.0/5.0 ns

Contextual Info: July 2001 Advance Information AS7C33512PFS16A AS7C33512PFS18A 3.3V 512K x 16/18 pipeline burst synchronous SRAM Features • Organization: 524,288 words × 16 or 18 bits • Fast clock speeds to 166 MHz in LVTTL/LVCMOS • Fast clock to data access: 3.5/3.8/4.0/5.0 ns

Contextual Info: July 2004 AS7C33512PFD18A 3.3V 512K x 18 pipeline burst synchronous SRAM Features • • • • • • • • • • • • • Organization: 524,288 words × 18 bits Fast clock speeds to 166 MHz in LVTTL/LVCMOS Fast clock to data access: 3.5/3.8/4.0/5.0 ns