AS7C33512PFD16A Search Results

Contextual Info: September 2001 Preliminary Information AS7C33512PFD16A AS7C33512PFD18A 3.3V 512K x 16/18 pipeline burst synchronous SRAM Features • Pentium®* compatible architecture and timing • Asynchronous output enable control • Economical 100-pin TQFP package

Contextual Info: March 2002 AS7C33512PFD16A AS7C33512PFD18A 3.3V 512K x 16/18 pipeline burst synchronous SRAM Features • Asynchronous output enable control • Available in 100-pin TQFP and 119-pin BGA package • Byte write enables • Multiple chip enables for easy expansion

Contextual Info: September 2001 Preliminary Information AS7C33512PFD16A AS7C33512PFD18A 3.3V 512K x 16/18 pipeline burst synchronous SRAM Features • Pentium®* compatible architecture and timing • Asynchronous output enable control • Economical 100-pin TQFP package

Contextual Info: Advance Information August 2001 AS7C33512PFD16A AS7C33512PFD18A 3.3V 512K x 16/18 pipeline burst synchronous SRAM Features • Pentium®* compatible architecture and timing • Asynchronous output enable control • Economical 100-pin TQFP package • Byte write enables

AS7C33512PFD16A

Abstract: AS7C33512PFD18A AS7C33512PFS16A AS7C33512PFS18A TMS320C6X
Contextual Info: April 2002 Preliminary AS7C33512PFD16A AS7C33512PFD18A 3.3V 512K x 16/18 pipeline burst synchronous SRAM Features • Asynchronous output enable control • Available in 100-pin TQFP and 119-pin BGA package • Byte write enables • Multiple chip enables for easy expansion

Contextual Info: November 2000 Advance Information AS7C33512PFS16A AS7C33512PFS18A 3.3V 512K x 16/18 pipeline burst synchronous SRAM Features • Organization: 524,288 words × 16 or 18 bits • Fast clock speeds to 166 MHz in LVTTL/LVCMOS • Fast clock to data access: 3.5/3.8/4.0/5.0 ns

Contextual Info: Advance Information August 2001 AS7C33512PFS16A AS7C33512PFS18A 3.3V 512K x 16/18 pipeline burst synchronous SRAM Features • Pentium®* compatible architecture and timing • Asynchronous output enable control • Economical 100-pin TQFP package • Byte write enables

Contextual Info: October 2001 Preliminary Information AS7C33512PFS16A AS7C33512PFS18A 3.3V 512K x 16/18 pipeline burst synchronous SRAM Features • Pentium®* compatible architecture and timing • Asynchronous output enable control • Economical 100-pin TQFP package

Contextual Info: July 2001 Advance Information AS7C33512PFS16A AS7C33512PFS18A 3.3V 512K x 16/18 pipeline burst synchronous SRAM Features • Organization: 524,288 words × 16 or 18 bits • Fast clock speeds to 166 MHz in LVTTL/LVCMOS • Fast clock to data access: 3.5/3.8/4.0/5.0 ns

Contextual Info: April 2002 Preliminary AS7C33512PFS16A AS7C33512PFS18A 3.3V 512K x 16/18 pipeline burst synchronous SRAM Features • • • • • • • • Asynchronous output enable control • Available in 100-pin TQFP and 119-ball BGA package • Byte write enables

Contextual Info: September 2001 Preliminary Information AS7C33512PFS16A AS7C33512PFS18A 3.3V 512K x 16/18 pipeline burst synchronous SRAM Features • Pentium®* compatible architecture and timing • Asynchronous output enable control • Economical 100-pin TQFP package

AS7C33512PFD16A

Abstract: AS7C33512PFD18A AS7C33512PFS16A AS7C33512PFS16A-166TQC AS7C33512PFS16A-166TQI AS7C33512PFS18A TMS320C6X
Contextual Info: March 2001 Advance Information AS7C33512PFS16A AS7C33512PFS18A 3.3V 512K x 16/18 pipeline burst synchronous SRAM Features • Organization: 524,288 words × 16 or 18 bits • Fast clock speeds to 166 MHz in LVTTL/LVCMOS • Fast clock to data access: 3.5/3.8/4.0/5.0 ns

AS7C33512PFD16A

Abstract: AS7C33512PFD18A AS7C33512PFS16A AS7C33512PFS18A TMS320C6X PENTIUM 1
Contextual Info: March 2002 AS7C33512PFS16A AS7C33512PFS18A 3.3V 512K x 16/18 pipeline burst synchronous SRAM Features • • • • • • • • Asynchronous output enable control • Available in 100-pin TQFP and 119-ball BGA package • Byte write enables • Multiple chip enables for easy expansion