54ALS139
Abstract: 74ALS139
Contextual Info: SN54ALS139, SN74ALS139 DUAL 2-LINE TO 4-LINE DECODERS/DEMULTIPLEXERS SO AS204A -AP R IL 1982 - REVISED DECEMBER 1994 Designed Specifically for High-Speed Memory Decoders and Data Transmission Systems Incorporate Two Enable Inputs to Simplify Cascading and/or Data Reception
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SN54ALS139,
SN74ALS139
AS204A
300-mll
54ALS139
74ALS139
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ACT7804-20
Abstract: SN74ACT7804 SN74ACT7806 SN74ACT7814
Contextual Info: SN74ACT7804 512x18 STROBED FIRST-IN, FIRST-OUT MEMORY S C A S 2 0 4 A -A P R IL 1992 - REVISED S E P TEM B E R 1995 Member of the Texas Instruments Widebus Family Load Clock and Unload Clock Can Be Asynchronous or Coincident 512 Words by 18 Bits Low-Power Advanced CMOS Technology
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SN74ACT7804
512x18
SCAS204A
50-pF
SN74ACT7806
SN74ACT7814
300-mil
25-mil
ACT7804-20
SN74ACT7804
SN74ACT7814
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SN74ACT7804
Abstract: SN74ACT7806 SN74ACT7814 LG5C 20G22
Contextual Info: SN74ACT7804 512 x 18 FIRST-IN, FIRST-OUT MEMORY SCAS204 -A P R IL 1992 DL PACKAGE TOP VIEW • Member of the Texas Instruments Widebus ,M Family • Load Clock and Unload Clock Can Be Asynchronous or Coincident RESET[ 1 D17 [ 2 • 512 Words by 18 Bits u
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SN74ACT7804
SCAS204
50-pF
SN74ACT7806
SN74ACT7814
300-mil
25-mil
lbl723
SN74ACT7804
SN74ACT7814
LG5C
20G22
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