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    ANTIFUSE PROGRAMMABLE CELL Search Results

    ANTIFUSE PROGRAMMABLE CELL Result Highlights (5)

    Part ECAD Model Manufacturer Description Download Buy
    AM27S25DM Rochester Electronics LLC OTP ROM Visit Rochester Electronics LLC Buy
    AM27C256-55PC Rochester Electronics LLC OTP ROM, Visit Rochester Electronics LLC Buy
    AMPAL20L10APC Rochester Electronics LLC PLD Visit Rochester Electronics LLC Buy
    AM27C010-55PI-G Rochester Electronics AM27C010 - EPROM - OTP, EPROM - UV 1Mbit 128k x 8 Visit Rochester Electronics Buy
    MC28F008-10/B Rochester Electronics LLC EEPROM, Visit Rochester Electronics LLC Buy

    ANTIFUSE PROGRAMMABLE CELL Datasheets Context Search

    Catalog Datasheet MFG & Type PDF Document Tags

    antifuse

    Abstract: actel act1 family ANTIFUSE-based actel antifuse programming technology
    Text: Back Actel and the Antifuse Page 1 of 5 Actel and the Antifuse • • • • • • • • Introduction Antifuse vs Memory-based Programmable Logic Antifuse Technology Evaluating Antifuse Alternatives User Benefits of Actel's PLICE Technology Future Directions in Antifuse Technology


    Original     		PDF

    CPGA routing

    Abstract: No abstract text available
    Text: pASIC 1 Family ViaLink Technology Very-High-Speed CMOS FPGAs FAMILY HIGHLIGHTS Very High Speed – ViaLink metal-to-metal, programmable-via antifuse technology ensures useful internal logic function speeds at over 100 MHz, and logic cell delays of under 2 ns.


    Original     		PDF 14-input QL8x12B MIL-STD-883D, CPGA routing

    ttl logic gates

    Abstract: pASIC 1 Family ttl and gate
    Text: pASIC 1 Family ViaLink Technology Very-High-Speed CMOS FPGAs FAMILY HIGHLIGHTS Very High Speed – ViaLink metal-to-metal, programmable-via antifuse technology ensures useful internal logic function speeds at over 100 MHz, and logic cell delays of under 2 ns.


    Original     		PDF 14-input MIL-STD-883D, ttl logic gates pASIC 1 Family ttl and gate

    Untitled

    Abstract: No abstract text available
    Text: QL8X12B pASIC 1 Family Very-High-Speed CMOS FPGA Rev B pASIC HIGHLIGHTS Very High Speed – ViaLink metal-to-metal programmable–via antifuse technology, allows counter speeds over 150 MHz and logic cell delays of under 2 ns. …1,000 usable ASIC gates,


    Original     		PDF QL8X12B 8-by-12 44-pin 68-pin 100-pin 16-bit Mentor144-TQFP QL24x32B 208-PQFP 208-CQFP

    QL8X12B

    Abstract: cmos ic and gates datasheet PF100
    Text: QL8X12B Wild Cat 1000 Very-High-Speed 1K 3K Gate CMOS FPGA Rev A .1000 usable gates, 64 I/O pins Very High Speed – ViaLinkTM metal-to-metal programmable–via antifuse technology, allows counter speeds over 150 MHz and logic cell delays of under 2 ns.


    Original     		PDF QL8X12B 8-by-12 44pin 68-pin 100-pin 16-bit 8x12B 44-pin PF100 QL8X12B cmos ic and gates datasheet PF100

    antifuse programming technology

    Abstract: ql24x32b PF144 PQ208 QL24X32B-1PQ208C
    Text: QL24x32B pASIC 1 Family Very-High-Speed CMOS FPGA pASIC HIGHLIGHTS …8,000 usable ASIC gates, 180 I/O pins Very High Speed – ViaLink metal-to-metal programmable–via antifuse technology, allows counter speeds over 150 MHz and logic cell delays of under 2 ns.


    Original     		PDF QL24x32B 24-by-32 144-pin 208-pin 24x32B PQ208 M/883C PF144 antifuse programming technology ql24x32b PF144 QL24X32B-1PQ208C

    ACTEL fpga

    Abstract: No abstract text available
    Text: The Actel Extender is a Secure Solution The antifuse and flash circuits that determine the configuration of Actel’s programmable devices are extremely secure because it is difficult to establish precisely how they are arranged in the silicon. The very small fuse elements and flash cells


    Original     		PDF

    QL8X12B

    Abstract: PF100 pASIC 1 Family circuit diagram of Tri-State Buffer using CMOS
    Text: QL8X12B pASIC 1 Family Very-High-Speed CMOS FPGA Rev B pASIC HIGHLIGHTS Very High Speed – ViaLink metal-to-metal programmable–via antifuse technology, allows counter speeds over 150 MHz and logic cell delays of under 2 ns. …1,000 usable ASIC gates,


    Original     		PDF QL8X12B 8-by-12 44-pin 68-pin 100-pin 16-bit QL8X12B PF100 pASIC 1 Family circuit diagram of Tri-State Buffer using CMOS

    FPGA 144 CPGA 172 PLCC ASIC

    Abstract: pASIC 1 Family 883-MIL
    Text: QL24x32B pASIC 1 Family Very-High-Speed CMOS FPGA pASIC HIGHLIGHTS …8,000 usable ASIC gates, 180 I/O pins Very High Speed – ViaLink metal-to-metal programmable–via antifuse technology, allows counter speeds over 150 MHz and logic cell delays of under 2 ns.


    Original     		PDF QL24x32B 24-by-32 144-pin 208-pin w144-TQFP 208-PQFP 208-CQFP 125oC FPGA 144 CPGA 172 PLCC ASIC pASIC 1 Family 883-MIL

    QL4090

    Abstract: No abstract text available
    Text: QL12X16B pASIC 1 Family Very-High-Speed CMOS FPGA Rev C pASIC HIGHLIGHTS …2,000 usable ASIC gates, 88 I/O pins Very High Speed – ViaLink metal-to-metal programmable–via antifuse technology, allows counter speeds over 150 MHz and logic cell delays of under 2 ns.


    Original     		PDF QL12X16B 12-by-16 68-pin 84-pin 100-pin 16-bit Synops144-TQFP QL24x32B 208-PQFP QL4090

    PF100

    Abstract: PL84 QL12X16B CPGA Package design 12x16B
    Text: QL12X16B pASIC 1 Family Very-High-Speed CMOS FPGA Rev C pASIC HIGHLIGHTS …2,000 usable ASIC gates, 88 I/O pins Very High Speed – ViaLink metal-to-metal programmable–via antifuse technology, allows counter speeds over 150 MHz and logic cell delays of under 2 ns.


    Original     		PDF QL12X16B 12-by-16 68-pin 84-pin 100-pin 16-bit 12x16B PF100 PL84 QL12X16B CPGA Package design

    PF144

    Abstract: PQ208 QL24X32B-1PQ208C
    Text: QL24x32B pASIC 1 Family Very-High-Speed CMOS FPGA pASIC HIGHLIGHTS …8,000 usable ASIC gates, 180 I/O pins Very High Speed – ViaLink metal-to-metal programmable–via antifuse technology, allows counter speeds over 150 MHz and logic cell delays of under 2 ns.


    Original     		PDF QL24x32B 24-by-32 144-pin 208-pin 24x32B PQ208 M/883C PF144 PF144 QL24X32B-1PQ208C

    QL24X32B-1PQ208C

    Abstract: PF144 PQ208
    Text: QL24x32B Wild Cat 8000 Very-High-Speed 8K 24K Gate CMOS FPGA 2 .8000 usable gates, 180 I/O pins Very High Speed – ViaLinkTM metal-to-metal programmable–via antifuse technology, allows counter speeds over 150 MHz and logic cell delays of under 2 ns.


    Original     		PDF QL24x32B 24-by-32 144pin 208-pin Viewlog-55, 24x32B PQ208 M/883C MIL-STD-883D PF144 QL24X32B-1PQ208C PF144

    100-Pin CPGA Package Pin-Out Diagram

    Abstract: 6.000 mhz QL12x16B-1PL68C 12x16B vqfp package pinout CF100 PF100 PL84 PV100 QL16X24B
    Text: QL12x16B Wild Cat 2000 Very-High-Speed 2K 6K Gate CMOS FPGA Rev B .2000 usable gates, 88 I/O pins Very High Speed – ViaLinkTM metal-to-metal programmable–via antifuse technology, allows counter speeds over 150 MHz and logic cell delays of under 2 ns.


    Original     		PDF QL12x16B 12-by-16 68pin 84-pin 100-pin 100pin 16-bit 12x16B 100-Pin CPGA Package Pin-Out Diagram 6.000 mhz QL12x16B-1PL68C vqfp package pinout CF100 PF100 PL84 PV100 QL16X24B

    pioneer PAL 005 A

    Abstract: K1603 FPGA 144 CPGA 172 PLCC ASIC VKS FPGA CQFP 106 8-bit interfacing ic 7447 AVNET uto 512 of 16-1 multiplexer BPW 40 pin connection in circuit
    Text: ACTLSOOl ACT 3 Field Programmable Gate Arrays Features Description • The ACT 3 family, based on Actel’s proprietary PLICE antifuse technology and 0.8-micron double-metal, double-poly CMOS process, offers a high-performance programmable solution capable of 167 MHz on-chip performance and 7.5 nanosecond


    OCR Scan     		PDF 20-pin pioneer PAL 005 A K1603 FPGA 144 CPGA 172 PLCC ASIC VKS FPGA CQFP 106 8-bit interfacing ic 7447 AVNET uto 512 of 16-1 multiplexer BPW 40 pin connection in circuit

    ttl and gate

    Abstract: No abstract text available
    Text: pASIC 1 Family ViaLink Technology Very-High-Speed CMOS FPGAs FAMILY HIGHLIGHTS Q Very High Speed - ViaLink metal-to-metal, programmable-via antifuse technology ensures useful internal logic function speeds at over 100 MHz, and logic cell delays of under 2 ns.


    OCR Scan     		PDF 14-input MIL-STD-883D, ttl and gate

    Untitled

    Abstract: No abstract text available
    Text: QL16X24 pASIC 1 FAMILY Very-High-Speed 4K 12K Gate CMOS FPGA ADVANCE DATA pASIC HIGHLIGHTS .4000 useable gates H Very High Speed - ViaLink metal-to-metal programmable-via antifuse technology, allows counter speeds over 100 MHz, and logic cell delays of undo: 4 ns.


    OCR Scan     		PDF QL16X24 16-by-24 16-bit 84-pin QL12xl6

    ic 431

    Abstract: QBS3
    Text: Q L 24x32B pASIC 1 Family Very-High-Speed CMOS FPGA pASIC HIGHLIGHTS .8,000 usable ASIC gates, 180 I/O pins Very High Speed - ViaLink® metal-to-metal programmable-via antifuse technology, allows counter speeds over 150 MHz and logic cell delays of under 2 ns.


    OCR Scan     		PDF 24x32B 24-by-32 144-pin 208-pin 24x32B PQ208 M/883C PF144 ic 431 QBS3

    Untitled

    Abstract: No abstract text available
    Text: Q L 8X 12B pASIC 1 Family Very-High-Speed CMOS FPGA Rev B pASIC HIGHLIGHTS Very High Speed - ViaLink" metal-to-metal programmable-via antifuse technology, allows counter speeds over 150 MHz and logic cell delays of under 2 ns. . 1,000 usable ASIC gates,


    OCR Scan     		PDF 8-by-12 44-pin 68-pin 100-pin 16-bit

    PL84C

    Abstract: CPGA Package Diagram TQFP 10 10
    Text: QL16x24B pASIC 1 Family Very-High-Speed CMOS FPGA Rev C pASIC HIGHLIGHTS .4,000 usable ASIC gates, 122 I/O pins Very High Speed - ViaLink" metal-to-metal programmable-via antifuse technology, allows counter speeds over 150 MHz and logic cell delays of under 2 ns.


    OCR Scan     		PDF QL16x24B 16-by-24 84-pin 100-pin 144-pin 160-pin 16-bit 16x24B PF144C PL84C CPGA Package Diagram TQFP 10 10

    Untitled

    Abstract: No abstract text available
    Text: QL12x16B WildCat 2000 Yery-High-Speed 2K 6K Gate CMOS FPGA Rev B pASIC HIGHLIGHTS .2000 usable gates, 88 I/O pins Very High Speed - ViaLink metal-to-metal programmable-via antifuse technology, allows counter speeds over 150 MHz and logic cell delays of under 2 ns.


    OCR Scan     		PDF QL12x16B 12-by-16 68pin 84-pin 100-pinCQFP, 100-pin 100pin 16-bit 12xl6B

    Untitled

    Abstract: No abstract text available
    Text: QL12x16BL pASIC 1 Family Low Power 3.3 Volt Operation FPGA pASIC HIGHLIGHTS High Speed - ViaLink" metal-to-metal programmable-via antifuse technology, allows counter speeds over 80 MHz at 3.3 Volt operation. 5Y Tolerant I/Os - Support interface to 5 Volt CMOS, NMOS and


    OCR Scan     		PDF QL12x16BL 12-by-16 68-pin 84-pin 100-pin QL12xl6B 12x16BL PF100

    Untitled

    Abstract: No abstract text available
    Text: QL16x24BL pASIC 1 Family Low Power 3.3 Volt Operation FPGA pASIC HIGHLIGHTS High Speed - ViaLink" metal-to-metal programmable-via antifuse technology, allows counter speeds over 80 MHz at 3.3 Volt operation. 5Y Tolerant I/Os - Support interface to 5 Volt CMOS, NMOS and


    OCR Scan     		PDF QL16x24BL 16-by-24 84-pin 100-pin 144-pin QL16x24B QL16X2VO 16X24BL F144C 84-pin

    Untitled

    Abstract: No abstract text available
    Text: QL8x12BL pASIC 1 Family Low Power 3.3 Volt Operation FPGA pASIC HIGHLIGHTS High Speed - ViaLink" metal-to-metal programmable-via antifuse technology, allows counter speeds over 80 MHz at 3.3 Volt operation. 5Y Tolerant I/Os - Support interface to 5 Volt CMOS, NMOS and


    OCR Scan     		PDF QL8x12BL 8-by-12 44-pin 68-pin 100-pin 8x12BL PL68C 68-pin PF100