16X24BL Search Results

PL84

Abstract: ql16x24bl PF100 PF144
Contextual Info: 16x24BL pASIC 1 Family Low Power 3.3 Volt Operation FPGA pASIC HIGHLIGHTS High Speed – ViaLink metal-to-metal programmable–via antifuse technology, allows counter speeds over 80 MHz at 3.3 Volt operation. 5V Tolerant I/Os – Support interface to 5 Volt CMOS, NMOS and

Contextual Info: 16X24BL pASIC 1 Family Low Power 3.3 Volt Operation FPGA pASIC HIGHLIGHTS .4,000 usable ASIC gates, 122 I/O pins S 5V Tolerant I/Os - Support interface to 5 Volt CMOS, NMOS and bipolar devices by sinking up to 12 mA see IIH specification . S High Usable Density - A 16-by-24 array of 384 logic cells

Contextual Info: 16x24BL pASIC 1 Family Low Power 3.3 Volt Operation FPGA pASIC HIGHLIGHTS High Speed - ViaLink" metal-to-metal programmable-via antifuse technology, allows counter speeds over 80 MHz at 3.3 Volt operation. 5Y Tolerant I/Os - Support interface to 5 Volt CMOS, NMOS and

Contextual Info: QL16x24B/QL16x24BH W ildcat 4000 Very-High-Speed 4K 12K Gate CMOS FPGA Rev B P Very High Speed - V ia L in k inetal-to-metal programmable-via anti­ fuse technology, allows counter speeds over 150 M H z and logic cell delays of under 2 ns. d .4000

PL84

Abstract: 4000 CMOS 4000L PF100 PF144
Contextual Info: 16x24BL Wild Cat 4000L Low Power 3.3 Volt Operation, 4K Gate FPGA 2 High Speed – ViaLinkTM metal-to-metal programmable–via antifuse technology, allows counter speeds over 80 MHz at 3.3 Volt operation. 5V Tolerant I/Os – Support interface to 5 Volt CMOS, NMOS and