CARSEM
Abstract: Lingsen Precision Industries AIT semicon lingsen
Text: Pericom Approved Manufacturing and Test Suppliers Company Name and Location Facility Type Pericom Semiconductor Corp., San Jose, CA Electrical Test Pericom Technology Inc., Shanghai, PRC Electrical Test Advanced Interconnect Technology AIT , Batam Island, Indonesia
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ITT semiconductors
Abstract: No abstract text available
Text: ADVANCE INFORMATION TPU 3042 Arabic/Hebrew Teletext Processor Edition Sept. 28, 1995 6251-416-2AI ITT Semiconductors TPU 3042 ADVANCE INFORMATION Contents Page Section Title 3 1. Introduction 3 2. Functional Description 3 4 5 8 9 10 3. 3.1. 3.2. 3.3. 3.4.
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6251-416-2AI
ITT semiconductors
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tpu3040
Abstract: No abstract text available
Text: ADVANCE INFORMATION TPU 3041 Cyrillic/Greek Teletext Processor Edition Sept. 27, 1995 6251-415-3AI ITT Semiconductors TPU 3041 ADVANCE INFORMATION Contents Page Section Title 3 3 4 1. 1.1. 1.2. Introduction Technical Code Change from TC19 to TC22 Software Incompatibility between Technical Codes 19 and 22
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6251-415-3AI
tpu3040
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dm74sl47
Abstract: DM74LS47N 54LS47DMQB 54LS47FMQB DM74LS47M J16A LS47 M16A N16E W16A
Text: National Ait Semiconductor 54LS47/DM74LS47 BCD to 7-Segment Decoder/Driver General Description Features The 'LS47 accepts four lines of BCD 8421 input data, gen erates their complements internally and decodes the data with seven AND/OR gates having open-coilector outputs to
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54LS47/DM74LS47
dm74sl47
DM74LS47N
54LS47DMQB
54LS47FMQB
DM74LS47M
J16A
LS47
M16A
N16E
W16A
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117 AJG
Abstract: No abstract text available
Text: PRELIMINARY CYPRESS SEMICONDUCTOR 128K Write-Through Secondary Cache Module Features Functional Description • 128-Kbyte d irect-m ap p ed , w ritethro u g h , zero-w ait-state secondary cache m odule • O p e ra tes w ith 33-M H z In tel 486 p ro cessors
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128-Kbyte
CYM7485
486-based
CYM7485
CYM7485ZPMâ
38-M-00058â
128-Pin
117 AJG
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80C251TB24
Abstract: A5001 A4532-02
Text: ADVANCE INFORMATION 8xC251 TA/TB/TP/TQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER Commercial/Express • Real-time and Programmed W ait State Bus Operation ■ Binary-code Com patible with MCSf 51 ■ Pin Com patible with 44-pin PLCC and 40-pin PDIP MCS 51 Sockets
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8xC251
44-pin
40-pin
40-byte
16-bit
32-bit
256-Kbyte
64-Kbyte
80C251TB24
A5001
A4532-02
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hd a101 pin configuration
Abstract: No abstract text available
Text: fax id: 1084 CY7C1334 64Kx32 Pipelined SRAM with NoBL Architecture Features • Low 16.5 mW standby power • Pin compatible and functionally equivalent to ZBT™ device MT55L64L32P • Supports 133-MHz bus operations with zero w ait states — Data is transferred on every clock
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CY7C1334
64Kx32
MT55L64L32P
133-MHz
100-MHz
r50-M
hd a101 pin configuration
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ZENER A23
Abstract: JP34-210-48 a23 zener JP35-200-18 JP23-100-48 JP23-100-18 Astec America
Text: ASTEC AMERICA/SEMICON] 5TE D • 1013155 OOOD&a2 2LM ■ AAI SEM ICONDUCTOR CIRCUITS, INC. SUBSIDIARY O F A STEO A M ER IC A , INC. JA/JP S eries 15 W ait DC/DC P ower C onverter S ingle , D ual , and T rifle O utputs F eatures M 4:1 Ultrawide input range
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fficiencyto85%
ZENER A23
JP34-210-48
a23 zener
JP35-200-18
JP23-100-48
JP23-100-18
Astec America
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pin diagram of ic 8086
Abstract: 8086 minimum mode and maximum mode timing diagram of 8086 maximum mode DMPAL16R4 dynamic ram system of 8088 microprocessor DP8409-2 Dp84432 DP8409 8086 minimum mode and maximum mode diagram intel 80186 pin out
Text: PRELIMINARY National Semiconductor O •o 00 u ro DP84432 Dynamic RAM Controller Interface Circuit for the 8086/8088/80186/80188 CPU s W orks w ith all 8086 fam ily speed ve rsio n s up to 10 MHz O peration o f 8086, 8088, 80186, 80188 at 10 M Hz with no W AIT states
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DP84432
DP84332,
DP8409A,
DP8429,
DP8419
DP840
tl/F/8399-6
pin diagram of ic 8086
8086 minimum mode and maximum mode
timing diagram of 8086 maximum mode
DMPAL16R4
dynamic ram system of 8088 microprocessor
DP8409-2
DP8409
8086 minimum mode and maximum mode diagram
intel 80186 pin out
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2N7805
Abstract: gw 340 diode t03 package transistor pin configuration 32N03 DTG2400 DTG-2400 2N2144A 2N1100 2N126 2n228 transistor
Text: CY7C1339 128K x 32 Synchronous-Pipelined Cache RAM Features The CY7C1339 I/O pins can operate at either the 2.5V or the 3.3V level; the I/O pins are 3.3V tolerant when V DDq=2.5V. * Supports 100-MHz bus fo r Pentium and PowerPC operations w ith zero w ait states
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CY7C1339
100-MHz
166-MHz
133-MHz
CY7C1339
Y220a/
T0220AA
T0220AB
TMW515TDB
2N7805
gw 340 diode
t03 package transistor pin configuration
32N03
DTG2400
DTG-2400
2N2144A
2N1100
2N126
2n228 transistor
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m3351
Abstract: KD 2114 marking code J2UT 1203 6d t201 CY7C1339 EQUIVALENT cd 1031 cs
Text: CY7C1339 128K x 32 Synchronous-Pipelined Cache RAM Features The CY7C1339 I/O pins can operate at either the 2.5V or the 3.3V level; the I/O pins are 3.3V tolerant when V DDq=2.5V. * Supports 100-MHz bus fo r Pentium and PowerPC operations w ith zero w ait states
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CY7C1339
100-MHz
166-MHz
133-MHz
CY7C1339
m3351
KD 2114
marking code J2UT
1203 6d
t201
EQUIVALENT cd 1031 cs
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Untitled
Abstract: No abstract text available
Text: I ''H New D ata, CD54/74HC597 CD54/74HCT597 lc - n Q - t t r File Number 27E D HARRIS SEMICOND SECTOR 1915 4302271 001Ô111 S High-Speed CMOS Logic 8-Bit Shift Register with Input Storage Type Features: 8P/F STO R A G E REG- a-aiT S H IF T REG. • B uffered Inputs
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CD54/74HC597
CD54/74HCT597
RCA-CD54/74HC597
CD54/74HCT597
43D2271
54/74HC
54/74HCT
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Untitled
Abstract: No abstract text available
Text: , ~ ~ 5 r PRELIMINARY CYPRESS SEMICONDUCTOR 32Kx 18 Synchronous Cache RAM • D irect in terface w ith th e p ro cesso r a n d extern al cach e con troller S u p p o rts 66-M H z P e n tiu m m icro p ro ce sso r cach e system s w ith zero w ait states
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intel core i7
Abstract: intel quad core i7 CY7C1327 CY7C1327-166AC
Text: fax id: 1107 CYPRESS CY7C1327 P R E L IM IN A R Y 256K X 18 Synchronous-Pipelined Cache RAM Features Functional Description Low 1.65 m W s ta n d b y p o w er (f= 0, L ve rs io n ) S u p p o rts 10 0-M H z bus fo r P en tiu m and Pow erPC o p e ratio n s w ith zero w ait sta tes
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CY7C1327
100-MHz
166-MHz
133-MHz
117-MHz
100-pin
intel core i7
intel quad core i7
CY7C1327
CY7C1327-166AC
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dip switch ece
Abstract: cs359
Text: I 3*427555 DD4T150 AIT • NECE N E C -DATA S H E E T . . BIPOLAR ANALOG INTEGRATED CIRCUIT ; E E C T R O N D E V IC E *’»> .» 4, . - »V -, it / / P C I 8 2 0 ' ; * ._t7 .7 ,.^ ?' COLOR TV/VTR PLL IF SIGNAL PROCESSING 1C The /¿PC1820 is a semiconductor integrated circuit for processing the color T V / V T R P IF / S IF signals. T his 1C is housed in a 30pin shrink dual-in-line package (D IP . Its main features are supported by the built-in keyed-pulse generator circuit needed for
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DD4T150
uPC1820
30pin
/zPC1820
30-pin
S30C-70-400B
dip switch ece
cs359
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ch 453d
Abstract: lo3b DP8430V lo3a oasi DP8431V DP8432V
Text: PRELIMINARY National M ay 1991 Semiconductor DP8430V/31V/32V-33 microCMOS Programmable 256k/1M /4M Dynamic RAM Controller/Drivers General Description Features Th e D P 8 4 3 0 V /3 1 V /3 2 V dynam ic RAM contro lle rs provide a low cost, single chip interface betw een dynam ic RAM and
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DP8430V/31V/32V-33
256k/1M/4M
DP8430V/31V/32V
32-bit
ch 453d
lo3b
DP8430V
lo3a
oasi
DP8431V
DP8432V
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asynchronous dram diagramed with explanation
Abstract: 8422a 308b microCMOS Programmable RF-208 DP8430V DP8431V DP8432V c31967 5253R10
Text: Semiconductor DP8430V/31V/32V-33 microCMOS Programmable 256k/1M /4M Dynamic RAM Controller/Drivers General Description Features The D P 8 4 3 0 V /3 1 V /3 2 V dynam ic RAM co ntro lle rs provide a low cost, single chip interface betw een dynam ic RAM and
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DP8430V/31V/32V-33
256k/1M/4M
DP8430V/31V/32V
32-bit
20-3A
asynchronous dram diagramed with explanation
8422a
308b
microCMOS Programmable
RF-208
DP8430V
DP8431V
DP8432V
c31967
5253R10
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tl 3042
Abstract: No abstract text available
Text: ADVANCE INFORMATION TPU 3042 Arabic/Hebrew Teletext Processor 4bö2711 0005S77 SÖ3 Edition Sept. 28, 1995 6251-416-2AI A ITT Semiconductors ITT TPU 3042 ADVANCE INFORMATION Contents Page Section Title 3 1. Introduction 3 2. Functional Description 3 4 5 8
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0005S77
6251-416-2AI
tl 3042
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Untitled
Abstract: No abstract text available
Text: Temic TSC80251G1D Semiconductors Extended 8-bit Microcontroller with Serial Communication Interfaces 1. Description to 256 Kbytes of external code and data. Additionally, the TSC83251G1D provides on-chip code memory 16 Kbytes ROM . The TSC80251G1D products are derivatives of the
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TSC80251G1D
TSC83251G1D
TSC80251G1D
87251G
-16IC
80251-SK
TSC80251
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MM4164
Abstract: DP8409 ns16032 Dynamic RAM Controller DMPAL16R6 NS16201 mm4164-12 NS16032-DP8409 MM5295 74s240
Text: ZWANational Æà Semiconductor p r e l im in a r y DP84312 Dynamic RAM Controller Interface Circuit for the NS16032 CPU General Description Features The DP84312 dyn am ic RAM c o n tro lle r in te rfa c e is a Pro gram m able Array Lo gic PAL * device w h ic h a llo w s fo r
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DP84312
NS16032
DP8409
NS16201
NS16032,
MM4164
Dynamic RAM Controller
DMPAL16R6
mm4164-12
NS16032-DP8409
MM5295
74s240
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Untitled
Abstract: No abstract text available
Text: fr | FORWARD INTERNATIONAL ELECTRONICS LTD, BC182 SEMICONDUCTOR NPN EPITAXIAL SILICON TRANSISTOR TECHNICAL DATA AMPLIFIER TRANSISTOR ABSOLUTE MAXIMUM RATINGS at Tairib=25‘c Symbol Vcbo R ating Unit 60 Vceo 50 V V Vebo 6 V Collector Diss^ation Ic Pc 100
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BC182
300uS
100uA
100mA
100mA
100uA
10VIe
100MHz
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4164-12
Abstract: DP8409 DMPAL16R6 ns16032
Text: DP84312 Dynamic Memory Support £51 National ÉlA Semiconductor PRELIMINARY DP84312 Dynamic RAM Controller Interface Circuit for the NS16032 CPU General Description Features The DP84312 dyn am ic RAM c o n tro lle r in te rfa c e Is a Pro gram m able A rray Logic PAL * device w h ic h a llo w s to r
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DP84312
DP84312
NS16032
DP8409
NS16201
NS16032,
4164-12
DMPAL16R6
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1301 dc he nv
Abstract: PB16-PB19 sedt SC02TH HP-47 PF30U
Text: MOTOROLA Order this document by: DSP56305/D SEMICONDUCTOR TECHNICAL DATA DSP56305 Advance Information SINGLE CHIP CHANNEL CODEC DIGITAL SIGNAL PROCESSOR Motorola designed the DSP56305 to deliver the high performance required to support Global System for Mobile GSM communications applications that use digital signal processing to
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DSP56305/D
DSP56305
DSP56305
DSP56300
AA0625
AA0626
1301 dc he nv
PB16-PB19
sedt
SC02TH
HP-47
PF30U
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7C601
Abstract: C32S CY7C325 C3253
Text: PRELIMINARY £25 CYPRESS SEMICONDUCTOR • Timing Control Unit, Clock Genera tor for CY7C601A and CY7C611A SPARC processors • Supports 25-, 33-, 40-MHz operation • Simplifies interface to slow memory and peripherals by eliminating the need for wait-state logic
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CY7C325
CY7C601A
CY7C611A
40-MHz
14-cycle
24-pin
300-mii
28-pin
7C601/611
7C601
C32S
CY7C325
C3253
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