AHB TO I2C Search Results

AHB TO I2C Result Highlights (5)

Part	Manufacturer	Description
ADC1038CIWM	Rochester Electronics LLC	ADC1038 - ADC, Successive Approximation, 10-Bit, 1 Func, 8 Channel, Serial Access, PDSO20
TL505CN	Rochester Electronics LLC	TL505 - Analog to Digital Converter
ML2258CIQ	Rochester Electronics LLC	ML2258 - ADC, Successive Approximation, 8-Bit, 1 Func, 8 Channel, Parallel, 8 Bits Access, PQCC28
CA3310AM	Rochester Electronics LLC	CA3310A - ADC, Successive Approximation, 10-Bit, 1 Func, 1 Channel, Parallel, Word Access, CMOS, PDSO24
CA3310M	Rochester Electronics LLC	CA3310 - ADC, Successive Approximation, 10-Bit, 1 Func, 1 Channel, Parallel, Word Access, CMOS, PDSO24

AHB TO I2C Datasheets Context Search

Catalog Datasheet	Type	Document Tags	PDF
stepper motor oki Abstract: BOSCH ECU microcontroller oki multi media card reader ML67Q2301 bosch can 2.0B OKI stepper motor BOSCH ECU information ecu repair ML67Q4003 ML67Q5003 Text: ARM-Based 32-bit RISC Microcontrollers Use Your Mind for Individuality. Use OKI for Universality. Introduction Dear Reader, Oki is the first company to incorporate ARM’s new higherspeed Advanced High Performance Bus AHB in its platform design. µPLAT provides system designers with	Original	32-bit ML671000 128-QFP ML674000 128-leadof F-94240 001-OEE-06/2003 stepper motor oki BOSCH ECU microcontroller oki multi media card reader ML67Q2301 bosch can 2.0B OKI stepper motor BOSCH ECU information ecu repair ML67Q4003 ML67Q5003	PDF
Untitled Abstract: No abstract text available Text: Freescale Semiconductor Technical Data MSC7116 Rev. 7, 10/2005 MSC7116 DMA 32 ch Trace Buffer (8 KB) ASEMI DSP Extended Core 64 AHB-Lite Crossbar Switch OCE SC1400 Core 64 to IPBus Fetch Unit Instruction Cache (16 KB) Extended Core Interface 128 M2 SRAM	Original	MSC7116 SC1400 HDI16 RS-232 SC1400	PDF
GPID-7 Abstract: GPIA10 duplex thermocouple C10C8 pcb MC711 GPIA21 Text: Freescale Semiconductor Technical Data MSC7116 Rev. 8, 12/2005 MSC7116 DMA 32 ch Trace Buffer (8 KB) ASEMI DSP Extended Core 64 AHB-Lite Crossbar Switch OCE SC1400 Core 64 to IPBus Fetch Unit Instruction Cache (16 KB) Extended Core Interface 128 M2 SRAM	Original	MSC7116 MSC7116 HDI16 RS-232 SC1400 HDI16) GPID-7 GPIA10 duplex thermocouple C10C8 pcb MC711 GPIA21	PDF
Untitled Abstract: No abstract text available Text: Freescale Semiconductor Technical Data MSC7116 Rev. 6, 4/2005 MSC7116 DMA 32 ch Trace Buffer (8 KB) ASEMI DSP Extended Core 64 AHB-Lite Crossbar Switch OCE SC1400 Core 64 to IPBus Fetch Unit Instruction Cache (16 KB) Extended Core Interface 128 M2 SRAM 64	Original	MSC7116 SC1400 HDI16 RS-232	PDF
verilog code for i2c Abstract: ahb to i2c verilog code verilog code for I2C MASTER verilog code for I2C MASTER slave i2c master verilog code atmel 8051 i2c sample code ahb to i2c design implementation 8051 I2C PROTOCOL 89C51IC2 verilog code for amba ahb master Text: I2C-HS Master/Slave Bus Controller Core The I2C-HS core implements a serial interface that meets the Philips I2C Bus specification version 2.1. It is compliant with the PVCI Peripheral Virtual Component Interface standard which is an open standard for SoC On-Chip Bus.	Original		PDF
89C51IC2 Abstract: 8051 THROUGH I2C PROTOCOL EP3SE50 ahb to i2c design implementation Text: I2C-HS Master/Slave Bus Controller Megafunction The I2C-HS megafunction implements a serial interface that meets the Philips I2C Bus specification version 2.1. It is compliant with the PVCI Peripheral Virtual Component Interface standard which is an open standard for SoC On-Chip Bus.	Original		PDF
3S100E-5 Abstract: 8051 THROUGH I2C PROTOCOL ahb to i2c design implementation 89C51IC2 "programmable clock" i2c texas ahb to i2c testbench of a transmitter in verilog Text: I2C-HS Master/Slave Bus Controller Core The I2C-HS core implements a serial interface that meets the Philips I2C Bus specification version 2.1. It is compliant with the PVCI Peripheral Virtual Component Interface standard which is an open standard for SoC On-Chip Bus.	Original		PDF
ARM926EJ-S Implementation Guide Abstract: ARM926EJ-S verilog coding for APB bridge state machine for ahb to apb bridge 8 pin AHB ARM926E-JS verilog code for amba ahb master AMBA 2.0 AHB to APB BUS Bridge verilog code AMBA AHB to APB BUS Bridge verilog code ARM926EJ-S jtag Text: DATASHEET 0.11 µm Processor System for ARM926EJ-S cw001200_agflxr_2_0 February 2005 Preliminary DB08-000261-01 This document is preliminary. As such, it contains data derived from functional simulations and performance estimates. LSI Logic has not verified either the	Original	ARM926EJ-STM cw001200 DB08-000261-01 cw001124 ARM926EJ-S Implementation Guide ARM926EJ-S verilog coding for APB bridge state machine for ahb to apb bridge 8 pin AHB ARM926E-JS verilog code for amba ahb master AMBA 2.0 AHB to APB BUS Bridge verilog code AMBA AHB to APB BUS Bridge verilog code ARM926EJ-S jtag	PDF
AMBA AXI to APB BUS Bridge vhdl code Abstract: PrimeCell AXI Configurable Interconnect PL300 Implementation Guide AMBA AXI to AhB BUS Bridge vhdl code PL081 AMBA AXI to AHB BUS Bridge verilog code axi wrapper 0x10018000 CT926EJ-S LF712 tsmc 0.18um Text: $SSOLFDWLRQ1RWH Using a CT7TDMI, CT926EJ-S or CT1136JF-S Core Tile with an Emulation Baseboard Document number: ARM DAI 0148D Issued: October 2007 Copyright ARM Limited 2007 $SSOLFDWLRQ1RWH	Original	CT926EJ-S CT1136JF-S 0148D AMBA AXI to APB BUS Bridge vhdl code PrimeCell AXI Configurable Interconnect PL300 Implementation Guide AMBA AXI to AhB BUS Bridge vhdl code PL081 AMBA AXI to AHB BUS Bridge verilog code axi wrapper 0x10018000 LF712 tsmc 0.18um	PDF
APB to I2C interface Abstract: spi controller with apb interface AMBA AHB DMA vhdl code for ddr sdram controller with AHB interface AMBA APB spi Cypress FX2 design of dma controller using vhdl ITU656 ahb to i2c SIMPLE VGA GRAPHIC CONTROLLER Text: LCD-Pro IP LCD-Pro IP modules DS0031 v1.01 – 20 July 2009 Datasheet: Table 1: Core Facts Implementation data Documentation Datasheet, User’s Manual Design File Formats EDIF netlist Constraint Files LPF file Reference Designs & Implementation examples	Original	DS0031 APB to I2C interface spi controller with apb interface AMBA AHB DMA vhdl code for ddr sdram controller with AHB interface AMBA APB spi Cypress FX2 design of dma controller using vhdl ITU656 ahb to i2c SIMPLE VGA GRAPHIC CONTROLLER	PDF
AN2548 Abstract: spi controller with apb interface STM32F10xxx AN2548 STM32F103 Text: AN2548 Application note Using the STM32F101xx and STM32F103xx DMA controller 1 Introduction This application note describes how to use the STM32F101xx and STM32F103xx direct memory access DMA controller. The STM32F101xx and STM32F103xx DMA controller, the Cortex -M3 core, the advanced microcontroller bus architecture (AMBA) bus and the	Original	AN2548 STM32F101xx STM32F103xx STM32F10xxx, AN2548 spi controller with apb interface STM32F10xxx AN2548 STM32F103	PDF
atmel h020 Abstract: atmel 0713 ATMEL 620 spear linux uart baud rate spear AA13 ARM926EJ-S MAC110 PBGA420 SPEAR-09-H022 Text: SPEAR-09-H022 SPEAr Head200 ARM 926, 200K customizable eASIC™ gates, large IP portfolio SoC PRELIMINARY DATA Features • ARM926EJ-S - fMAX 266 MHz, 32 KI - 16 KD cache, 8 KI - KD TCM, ETM9 and JTAG interfaces ■ 200K customizable equivalent ASIC gates	Original	SPEAR-09-H022 Head200 ARM926EJ-S PBGA420 atmel h020 atmel 0713 ATMEL 620 spear linux uart baud rate spear AA13 MAC110 PBGA420 SPEAR-09-H022	PDF
SPEAR-09-B042 Abstract: Camera Module CSI2 interface Mobile Camera Module motorola l7 8202 dram controller GPIO109 lpddr ARM926EJ-S ITU656 41 942 RGB565 to rgb888 epson Text: SPEAR-09-B042 SPEAr BASIC ARM 926EJ-S core, customizable logic, large IP portfolio SoC Preliminary Data Features • ARM926EJ-S core @333 MHz – 16 Kbyte instructions/data cache ■ Reconfigurable logic array: – 300 Kgate 100% utilization rate – 102 I/O lines	Original	SPEAR-09-B042 926EJ-S ARM926EJ-S LFBGA289 32-Kbyte 10-bit, SPEAR-09-B042 Camera Module CSI2 interface Mobile Camera Module motorola l7 8202 dram controller GPIO109 lpddr ITU656 41 942 RGB565 to rgb888 epson	PDF
atmel h020 Abstract: atmel 0713 AA13 ARM926EJ-S MAC110 PBGA420 SPEAR-09-H022 usb 3 sm Flash drive controller M25Pxxx state machine for ahb to apb bridge Text: SPEAR-09-H022 SPEAr Head200 ARM 926, 200K customizable eASIC™ gates, large IP portfolio SoC PRELIMINARY DATA Features • ARM926EJ-S - fMAX 266 MHz, 32 KI - 16 KD cache, 8 KI - KD TCM, ETM9 and JTAG interfaces ■ 200K customizable equivalent ASIC gates	Original	SPEAR-09-H022 Head200 ARM926EJ-S PBGA420 atmel h020 atmel 0713 AA13 MAC110 PBGA420 SPEAR-09-H022 usb 3 sm Flash drive controller M25Pxxx state machine for ahb to apb bridge	PDF

AN2564 Abstract: AN2548 cortex m3 amba bus architecture Text: AN2548 Application note Using the STM32F101xx and STM32F103xx DMA controller 1 Introduction This application note describes how to use the STM32F101xx and STM32F103xx direct memory access DMA controller. The STM32F101xx and STM32F103xx DMA controller, the Cortex -M3 core, the advanced microcontroller bus architecture (AMBA) bus and the	Original	AN2548 STM32F101xx STM32F103xx STM32F10xxx, AN2564 AN2548 cortex m3 amba bus architecture	PDF
atmel h020 Abstract: atmel h022 atmel 0713 0x16000000 Atmel PART DATE CODE AA13 ARM926EJ-S MAC110 PBGA420 SPEAR-09-H022 Text: SPEAR-09-H022 SPEAr Head200 ARM 926, 200K customizable eASIC™ gates, large IP portfolio SoC Features • ARM926EJ-S - fMAX 266 MHz, 32 KI - 16 KD cache, 8 KI - KD TCM, ETM9 and JTAG interfaces ■ 200K customizable equivalent ASIC gates 16K LUT equivalent with 8 channels internal	Original	SPEAR-09-H022 Head200 ARM926EJ-S 16-bit atmel h020 atmel h022 atmel 0713 0x16000000 Atmel PART DATE CODE AA13 MAC110 PBGA420 SPEAR-09-H022	PDF
H122 Abstract: ph6n PH5N ph8n transistor PH6n ph7n ph4n ARMv5TEJ 0xE12 E31821 Text: SPEAR-09-H122 SPEAr Head600 Preliminary Data Features • ARM926EJ-S core @333MHz. ■ 600KByte reconfigurable logic array with 88 dedicated General purposes I/Os, 9 LVDS channels and 128KByte configurable internal memory pool. ■ Multilayer AMBA 2.0 compliant Bus with fMAX	Original	SPEAR-09-H122 Head600 ARM926EJ-S 333MHz. 600KByte 128KByte 166MHz 32KByte 8/16bit 200MHz) H122 ph6n PH5N ph8n transistor PH6n ph7n ph4n ARMv5TEJ 0xE12 E31821	PDF
atmel h020 Abstract: M25Pxxx state machine for ahb to apb bridge multiport memory controller A13 cristal ARM926EJ-S electrical ATMEL 0905 INPUT/atmel h020 Text: SPEAr-09-H020 SPEAr Head ARM 926, 200K customizable eASIC™ gates, large IP portfolio SoC PRELIMINARY DATA Features • ARM926EJ-S - fMAX 266 MHz, 32 KI - 16 KD cache, 8 KI - KD tcm, ETM9 and JTAG interfaces ■ 200K customizable equivalent ASIC gates with	Original	SPEAr-09-H020 ARM926EJ-S atmel h020 M25Pxxx state machine for ahb to apb bridge multiport memory controller A13 cristal ARM926EJ-S electrical ATMEL 0905 INPUT/atmel h020	PDF
PH6n Abstract: ph5n ph8n Text: SPEAR-09-P022 SPEAr Plus600 dual processor cores Preliminary Data Features • Dual ARM926EJ-S core @333MHz. ■ 600KByte reconfigurable logic array with 88 dedicated General purposes I/Os, 9 LVDS channels and 128KByte configurable internal memory pool.	Original	SPEAR-09-P022 Plus600 ARM926EJ-S 333MHz. 600KByte 128KByte 166MHz 32KByte 8/16bit 200MHz) PH6n ph5n ph8n	PDF
ph5n Abstract: "ph4n" ph6n UART TTL buffer ph0n DDRDATA11 kss3k Text: SPEAR-09-H122 SPEAr Head600 Preliminary Data Features • ARM926EJ-S core @333MHz. ■ 600KByte reconfigurable logic array with 88 dedicated General purposes I/Os, 9 LVDS channels and 128KByte configurable internal memory pool. ■ Multilayer AMBA 2.0 compliant Bus with fMAX	Original	SPEAR-09-H122 Head600 ARM926EJ-S 333MHz. 600KByte 128KByte 166MHz 32KByte 8/16bit 200MHz) ph5n "ph4n" ph6n UART TTL buffer ph0n DDRDATA11 kss3k	PDF
lqfp64 Abstract: LQFP64 package ARM7 LPC2138 LQFP-64 ARM7TDMI-S pll nxp lpc2138 32 KB SRAM 16C550 LPC2131 LPC2132 Text: 60-MHz, 32-bit microcontroller with ARM7TDMI-S core LPC213x ARM7-based microcontrollers with two 10-bit ADCs and 10-bit DAC These powerful yet cost-effective microcontrollers have up to 512 KB of ISP/IAP Flash and up to 32 KB of SRAM. Each has up to two 10-bit A/D converters, a 10-bit D/A converter, two I2C-bus	Original	60-MHz, 32-bit LPC213x 10-bit 32-bit LPC213x/01 lqfp64 LQFP64 package ARM7 LPC2138 LQFP-64 ARM7TDMI-S pll nxp lpc2138 32 KB SRAM 16C550 LPC2131 LPC2132	PDF
ph4n Abstract: PH5N ph6n transistor PH6n DDR2-333 H122 ph8n transistor PH7n tms1040 V/transistor ph4n Text: SPEAR-09-H122 SPEAr Head600 Preliminary Data Features • ARM926EJ-S core @333 MHz ■ 600 Kbyte reconfigurable logic array with 88 dedicated general purposes I/Os, 9 LVDS channels and 128 Kbyte configurable internal memory pool ■ Multilayer AMBA 2.0 compliant bus with fMAX	Original	SPEAR-09-H122 Head600 ARM926EJ-S 8/16-bit ph4n PH5N ph6n transistor PH6n DDR2-333 H122 ph8n transistor PH7n tms1040 V/transistor ph4n	PDF
atmel h020 Abstract: atmel h022 uart baud rate spear AA13 ARM926EJ-S MAC110 PBGA420 SPEAR-09-H022 Atmel ARM9 ATMEL 0905 Text: SPEAR-09-H022 SPEAr Head ARM 926, 200K customizable eASIC™ gates, large IP portfolio SoC PRELIMINARY DATA Features • ARM926EJ-S - fMAX 266 MHz, 32 KI - 16 KD cache, 8 KI - KD tcm, ETM9 and JTAG interfaces ■ 200K customizable equivalent ASIC gates	Original	SPEAR-09-H022 ARM926EJ-S PBGA420 atmel h020 atmel h022 uart baud rate spear AA13 MAC110 PBGA420 SPEAR-09-H022 Atmel ARM9 ATMEL 0905	PDF
80C552 Abstract: No abstract text available Text: Uses two wires to transfer information between devices o Serial Clock Line SCL SCL I2CS Slave Bus Controller Megafunction The I2CS Bus Controller logic provides a serial interface that meets the Philips I2C bus specification and supports all slave transfer modes to and from the I2C bus. The I2CS	Original	EP1S10-5 80C552	PDF

AHB TO I2C Search Results

AHB TO I2C Result Highlights (5)

AHB TO I2C Datasheets Context Search

stepper motor oki

Untitled

GPID-7

Untitled

verilog code for i2c

89C51IC2

3S100E-5

ARM926EJ-S Implementation Guide

AMBA AXI to APB BUS Bridge vhdl code

APB to I2C interface

AN2548

atmel h020

SPEAR-09-B042

atmel h020

AN2564

atmel h020

H122

atmel h020

PH6n

ph5n

lqfp64

ph4n

atmel h020

80C552