A54SXA Search Results

1553b VHDL

Abstract: Actel 1553b fpga 1553B transistor BC 584 MIL-STD-1553B FPGA RT MIL-STD-1553B ACTEL FPGA manchester verilog decoder vhdl code manchester encoder mil-std-1553b SPECIFICATION transistor BC 490
Contextual Info: Core1553BBC MIL-STD-1553B Bus Controller Product Summary • Intended Use • 1553B Bus Controller BC • DMA Backend Interface to External Memory Synthesis and Simulation Support Key Features • • • • • • Supports MIL-STD-1553B Interfaces to External RAM

LGA 478 SOCKET PIN LAYOUT

Abstract: RTAX2000
Contextual Info: v5.2 RTAX-S/SL RadTolerant FPGAs Radiation Performance Leading-Edge Performance • • • • • • • • • • SEU-Hardened Registers Eliminate the Need for TripleModule Redundancy TMR – Immune to Single-Event Upsets (SEU) to LETTH > 37 MeV-cm2/mg

RTAX2000

Abstract: rtax4000 CDB 455 C34 IO358 DIODE SMD V05 128X3
Contextual Info: v5.1 RTAX-S/SL RadTolerant FPGAs Radiation Performance Leading-Edge Performance • • • • • • • • • • SEU-Hardened Registers Eliminate the Need for TripleModule Redundancy TMR – Immune to Single-Event Upsets (SEU) to LETTH > 37 MeV-cm2/mg

types of trees in data structure

Abstract: AC198 A54SXA RT54SX-S timing analysis example Signal Path Designer RTAX-S library
Contextual Info: Application Note AC198 Clock Skew and Short Paths Timing Clock Skew Differences in clock signal arrival times across the chip are called clock skew. It is a fundamental design principle that timing must satisfy register setup and hold time requirements. Both data propagation delay

SIGNAL PATH DESIGNER

Contextual Info: Viewlogic Powerview Interface Guide UNIX® Environments Actel Corporation, Sunnyvale, CA 94086 2000 Actel Corporation. All rights reserved. Printed in the United States of America Part Number: 5579003-4 Release: July 2000 No part of this document may be copied or reproduced in any form or by

SIGNAL PATH designer

Abstract: 1623G
Contextual Info: Innoveda eProduct Designer Interface Guide UNIX ® Environments Actel Corporation, Sunnyvale, CA 94086 2001 Actel Corporation. All rights reserved. Printed in the United States of America Part Number: 5579030-0 Release: February 2001 No part of this document may be copied or reproduced in any form or by any

RTAX1000S-STD

Abstract: fpga 1553B 1553b VHDL RTAX1000S V203M manchester verilog decoder MIL-STD-1553B FPGA vhdl code manchester encoder MIL-HDBK-1553A 553B
Contextual Info: v2.0 MIL-STD-1553B Bus Controller Core1553BBC Pr od uc t S um m ary S ynt he si s and S im ul ati on S uppor t In t e n d e d Us e • Synthesis: Exemplar, Synplicity, Design Compiler, FPGA Compiler, FPGA Express • 1553B Bus Controller BC • DMA Backend Interface to External Memory

RTAX1000SL

Abstract: RTAX1000S RTAX1000S-SL RTAX250SL RTAX2000SL RTAX2000S RTAX250S RTAX4000S 56 pin edac connector
Contextual Info: RTAX-S/SL RadTolerant FPGAs Detailed Specifications Table 2-1 • I/O Features Comparison I/O Assignment 3.3 V LVTTL Clamp Diode Hot Insertion / Cold Sparing 1 Yes 5V Tolerance Input Buffer Output Buffer No 1 Yes Enabled/Disabled Enabled/Disabled 3.3 V PCI

Contextual Info: Revision 16 RTAX-S/SL and RTAX-DSP Radiation-Tolerant FPGAs Radiation Performance Specifications • SEU-Hardened Registers Eliminate the Need for Triple-Module Redundancy TMR – Immune to Single-Event Upsets (SEU) to LETTH > 37 MeVcm2/mg – SEU Rate < 10-10 Errors/Bit-Day (worst case GEO)

RTAX2000

Abstract: ProASIC3 A3P250 RTAX1000S A3P125 A54SX16A A54SX32A APA075 AX125 PAR64 RTAX250S
Contextual Info: CorePCI v5.41 Product Summary Synthesis and Simulation Support Intended Use • Most Flexible High-Performance PCI Offering – Synthesis: ExemplarTM, Synopsys DC / FPGA CompilerTM, and Synplicity® • Simulation: Vital-Compliant VHDL Simulators and OVI- Compliant Verilog Simulators

Contextual Info: VHDL VITAL Simulation Guide Windows and UNIX® Environments Actel Corporation, Sunnyvale, CA 94086 2000 Actel Corporation. All rights reserved. Printed in the United States of America Part Number: 5579006-4 Release: July 2000 No part of this document may be copied or reproduced in any form or by

Signal Path Designer

Contextual Info: Mentor Graphics Interface Guide R1-2002 UNIX ® Environments Actel Corporation, Sunnyvale, CA 94086 2002 Actel Corporation. All rights reserved. Printed in the United States of America Part Number: 5579001-7 Release: June 2002 No part of this document may be copied or reproduced in any form or by any

RTAX2000

Abstract: RTAX2000S RTAX1000SL rtax250 RTAX250SL RTAX4000SL RTAX1000 RTAX-S RTAX1000S-SL rtax250s
Contextual Info: Rev ision 13 RTAX-S/SL and RTAX-DSP Radiation-Tolerant FPGAs Radiation Performance Specifications • SEU-Hardened Registers Eliminate the Need for Triple-Module Redundancy TMR – Immune to Single-Event Upsets (SEU) to LETTH > 37 MeVcm2/mg – SEU Rate < 10-10 Errors/Bit-Day (worst case GEO)

54SX72

Abstract: actel act1 family signal path designer
Contextual Info: Actel Getting Started User’s Guide R1-2002 Windows ® and UNIX ® Environments For more information about Actel’s products, call 888-99-ACTEL or visit our Web site at http://www.actel.com Actel Corporation • 955 East Arques Avenue • Sunnyvale, CA USA 94086

1200X

Abstract: signal path designer Silicon Sculptor II
Contextual Info: Cadence Interface Guide UNIX® Environments For more information about Actel’s products, call 888-99-ACTEL or visit our Web site at http://www.actel.com Actel Corporation • 955 East Arques Avenue • Sunnyvale, CA USA 94086 U.S. Toll Free Line: 888-99-ACTEL • Customer Service: 408-739-1010 • Customer Service FAX: 408-522-8044

A54SXA

Abstract: A54SX-A PD30111 A54SX16A
Contextual Info: v3.0 CorePCI Target, Master, and Master/Target Pr od uc t S um m ary In t e n d e d U s e • High-Performance PCI Applications Mac ro Ve ri fica ti on and Com p li ance • Actel-Developed Test Bench • Hardware Tested – Target, Master, and Master/Target, which includes

Contextual Info: Verilog Simulation Guide R1-2002 Windows ® and UNIX ® Environments Actel Corporation, Sunnyvale, CA 94086 2002 Actel Corporation. All rights reserved. Printed in the United States of America Part Number: 5579005-7 Release: June 2002 No part of this document may be copied or reproduced in any form or by any

w32 smd transistor

Abstract: rtax250sl RTAX2000S w32 smd transistor 143 41-bit Carry Look-ahead Adder RTAX2000SL RTAX4000S BY415 RTAX4000D LG1152
Contextual Info: Revision 14 RTAX-S/SL and RTAX-DSP Radiation-Tolerant FPGAs Radiation Performance Specifications • SEU-Hardened Registers Eliminate the Need for Triple-Module Redundancy TMR – Immune to Single-Event Upsets (SEU) to LETTH > 37 MeVcm2/mg – SEU Rate < 10-10 Errors/Bit-Day (worst case GEO)

LG1152

Abstract: ACTEL CCGA 624 mechanical A54SXA LG1272 CQ352
Contextual Info: v5.3 RTAX-S/SL RadTolerant FPGAs Radiation Performance Leading-Edge Performance • • • • • • • • • • SEU-Hardened Registers Eliminate the Need for TripleModule Redundancy TMR – Immune to Single-Event Upsets (SEU) to LETTH > 37 MeV-cm2/mg

CQ352-FPGA

Abstract: RTAX1000s-cq RTAX4000S RTAX2000 RTAX2000S-CQ352 FPGA Application Note schematic 324 CDB 455 C34 rtax4000 AP3433
Contextual Info: v4.0 RTAX-S RadTolerant FPGAs Designed for Space • • • • • • • SEU-Hardened Registers Eliminate the Need for Triple-Module Redundancy TMR – Immune to Single-Event Upsets (SEU) to LETTH > 37 MeV-cm2/mg – SEU Rate < 10-10 Errors/Bit-Day in Worst-Case

VHDL CODE FOR HDLC controller

Abstract: A54SXA FCS-16 MDS300 HDLC verilog code A3P250 A54SX16A APA075 crc verilog code 16 bit design of HDLC controller using vhdl
Contextual Info: AvnetCore: Datasheet Version 1.0, July 2006 Single-Channel HDLC Controller Intended Use: — Frame Relay — ISDN and X.25 protocols — Logic consolidation Features: — Conforms to International Standard ISO/IEC 3309 Specification External Logic I Pad I Pad

RTAX2000D

Abstract: LG1152 CDB 455 C34
Contextual Info: Revision 14 RTAX-S/SL and RTAX-DSP Radiation-Tolerant FPGAs Radiation Performance Specifications • SEU-Hardened Registers Eliminate the Need for Triple-Module Redundancy TMR – Immune to Single-Event Upsets (SEU) to LETTH > 37 MeVcm2/mg – SEU Rate < 10-10 Errors/Bit-Day (worst case GEO)

624 CCGA

Abstract: CQ352 transistor prc 606 j rtax250 RTAX2000 rtax4000
Contextual Info: Revision 14 RTAX-S/SL and RTAX-DSP Radiation-Tolerant FPGAs Radiation Performance Specifications • SEU-Hardened Registers Eliminate the Need for Triple-Module Redundancy TMR – Immune to Single-Event Upsets (SEU) to LETTH > 37 MeVcm2/mg – SEU Rate < 10-10 Errors/Bit-Day (worst case GEO)

ACTEL CCGA 624 mechanical

Abstract: LG1152 RTAX2000S ACTEL burn-in RTAX250S LGA 2011 Socket diagram RTAX2000 ACTEL CCGA 1152 mechanical cg624 RTAX1000S
Contextual Info: v5.4 RTAX-S/SL RadTolerant FPGAs Radiation Performance Leading-Edge Performance • • • • • • • • • • SEU-Hardened Registers Eliminate the Need for TripleModule Redundancy TMR – Immune to Single-Event Upsets (SEU) to LETTH > 37 MeV-cm2/mg