A12Q Search Results

Contextual Info: TEXAS INSTR {ASIC/nEHORY} PRODUCT PREVIEW 77 dT | AGITES 0040^40 5 TMX27PC128 131,072-BIT PROGRAMMABLE READ ONLY M EM O RY N O V E M B E R 1985 x 8 TOP VIEW vppC Pin C om patible w ith E xistin g 6 4 K and 1 2 8 K EPROM s 1 ^J28 A12Q 2 A7C A6C A ll Inputs/O utputs Fully T T L Com patible

27pc256

Abstract: TMS27PC256 26HA13
Contextual Info: ADVANCE INFORMATION ^ fOt ¿r-I / o 7 L-Cf ^ TMS27PC256 W ? 262,144-BIT PROGRAMMABLE READ-ONLY M E M O R Y ^ ï-P-' N O V EM B ER 1985 - R EV IS E D A U G U S T 1986 Organization . . . 3 2 K x 8 N PACKAGE {T O P V IE W Single 5-V Pow er Supply Vpp[_ A12Q

NCC equivalent

Contextual Info: TMS29F400T, TMS29F400B 524288 BY 8-BIT/262144 BY 16-BIT FLASH M EMORIES • I • Single Power Supply Supports 5 V ± 10% Read/Write Operation I I • Organization . . . I • Array-Blocking Architecture - One 16K-Byte/One 8K-Word Boot Sector - Two 8K-Byte/4K-Word Parameter Sectors

Contextual Info: TMS28F008Axy,TMS28F800Axy 1 048 576 BY 8-BIT/524 288 BY 16-BIT AUTO-SELECT BOOT-BLOCK FLASH MEMORIES SM JS851A-NO VEM BER 1997 - REVISED MARCH 1998 • Organization . . . 1048576 By 8 Bits 524288 By 16 Bits • Array-Blocking Architecture - Two 8K-Byte/4K-Word Parameter Blocks

ALY 34

Abstract: 28f800 TMS2800 R-PDSO-G44 Package A10q ALY-34
Contextual Info: TMS28F008Axy,TMS28F800Axy 1 048 576 BY 8-BIT/524 288 BY 16-BIT AUTO-SELECT BOOT-BLOCK FLASH MEMORIES S M JS 851A - N O VEM BER 1997 - REVISED M ARCH 1998 Organization . . . 1048576 By 8 Bits 524288 By 16 Bits Array-Blocking Architecture - Two 8K-Byte/4K-Word Parameter Blocks

rca thyristor manual

Abstract: HN623258 101490
Contextual Info: Quick Reference Guide to Hitachi 1C Memories Package Information Reliability of Hitachi 1C Memories Applications MOS Static RAM MOS Pseudo Static RAM Application Specific Memory MOS Dynamic RAM MOS Dynamic RAM Module MOS Mask ROM MOS PROM ECL RAM P> Jc^< j

Contextual Info: Preliminary . / * < > • ^ „ LG Sem icon CO.,Ltd. G M 7 2 V 2 8 4 4 1 A T /A L T 8,388,608 WORD x 4 BIT x 4 BANK SYNCHRONOUS DYNAMIC RAM Description TheGM72V28441 AT/ALT is a synchronous dynamic random access memory comprised of 134,217,728 memory cells and logic

Contextual Info: HN623257P, HN623257F 32768-word x 8-bit CMOS Mask Programmable Read Only Memory Th e H N 6 2 3 2 5 7 P /F is a 2 5 6 -k b it C M OS mask-programmable R O M organized as 3 2 7 6 8 words by 8 bits. HN 623257P Realizing low power consumption, this m em ory is allowed fo r battery operation.

27PC128

Contextual Info: PRODUCT PREVIEW TMX27PC128 131.072-BIT PROGRAMMABLE READ ONLY MEMORY N O V E M B E R 1985 N PACKAGE TOP VIEW vppC 3 vcc • Pin Compatible with Existing 64K and 128K EPRO M s All Inputs/Outputs Fully TTL Compatible A7C 3 26 3 A 1 3 • A 6£ 4 25 J A 8 •

2732A eprom

Abstract: intel 2764 2764 2764 pin diagram INTEL 2764 EPROM ROM 2764 2764 eprom PINOUT pRoM 2764 EPROM 2764 2764 rom
Contextual Info: in te T 2764 8K x 8 UV ERASABLE PROM • Pin Compatible to 2732A EPROM 200 ns (2764-2) Maximum Access Time . . . HMOS*-E Technology ■ Industry Standard P inout. . . JEOEC Approved Compatible to High Speed 8mHz 8086-2 MPU . . . Zero WAIT State ■ Low Active Current.!00mA Max.

MBM27C256A-20CZ

Abstract: MB89P
Contextual Info: • DESCRIPTION The MB89910 series has been developed as a general-purpose version £>f the F2MC*^8 L fam ily consisting of proprietary 8-bit, single-chip microcontrollers. In addition to a compact instruction set, the microcontrollers contain'a variety of peripheral functions such as

Contextual Info: mV Y "fi I II II il A U R U I H Y 6 3 V 8 1 0 0 A S /H Y 6 3 V 8 1 O O A L 128K X 8 B it I l l FAST SRAM PRELIMINARY DESCRIPTION The HY63V8100 is a 1,048,576 -bits high-speed Static Random Access Memory organized as 131,072 words by 8 bits. The HY63V8100 uses eight common input and output lines and has an output enable pin which operates

A12Q

Contextual Info: Creation Date: July 31, 1998 Revision: October 7, 1998 ptos • s e m ic o n d u c t o r PRELIMINARY A P 9 A 1 1 4 /A P 9 A 1 1 4 L 5V, 64K x 16, Very High-Speed, Low-Power, CMOS Static RAM with Optional 2V Data Retention Features • • • • • • •

Contextual Info: TMS28F004Axy, TMS28F400Axy 52 42 88 BY 8-B IT/262144 BY 16-BIT AUTO-SELECT BOOT-BLOCK FLASH MEMORIES SMJS829A - JANUARY 1996 - REVISED AUGUST 1997 • Organization . . . 524288 By 8 Bits 262144 By 16 Bits • Array-Blocking Architecture - One 16K-Byte Protected Boot Block

O09P

Contextual Info: TMS29LF400T, TMS29LF400B 524288 BY 8-BIT/262144 BY 16-BIT FLASH MEMORIES • • • • • • • • • 524288 By 8 Bits 262144 By 16 Bits Array-Blocking Architecture - One 16K-Byte/One 8K-Word Boot Sector - Two 8K-Byte/4K-Word Parameter Sectors - One 32K-Byte/16K-Word Sector

a14q

Contextual Info: TMS28F008SET, TMS28F008SEB, TMS28F800SET. TMS28F800SEB TMS28F008SZT, TMS28F008SZB, TMS28F800SZT, TMS28F800SZB 1048576 BY 8-BJT/524288 BY 16-BIT BOOT-BLOCK FLASH MEMORIES • • • • • • • • Organization. . . 1048576 By 8 Bits 524288 By 16 Bits

pc 2561

Abstract: S27C256 27PC256NL
Contextual Info: TMS27C256 262.144-BIT UV ERASABLE PROGRAMMABLE READ-ONLY MEMORY TMS27PC256 262,144-BIT PROGRAMMABLE READ-ONLY MEMORY SEPTEMBER 1 9 8 4 -REVISED MARCH 1988 This Data Sheet is Applicable to A ll TMS27C256S a nd TMS27PC256s Sym bolized w ith Code " A " as Described on Page 12.

2764 eprom PINOUT

Abstract: 4Kx8 sram ttl 2764 RAM 4Kx8 rom ttl 4kx8 sram INTEL 2764 EPROM INTEL 2764 SRAM 4KX8 4kx8 static ram ttl 2Kx8 SRAM
Contextual Info: A O M IN ! OMIF©fôlîMïrD@Kl in te i 2048 X 2K X 8 8-BIT STATIC RAM Fully Static Operation; No Clocks, Refresh or Latches Two Line Control, CE Controls PowerDown, OE Controls Output Buffers — Eliminates Bus Contention EPROM Compatible Pinout 150 ns Maximum Access Time

ad9a

Contextual Info: Preliminary MXIC MX23L6410 64M-Bit Mask ROM 8/16 Bit Output O R D E R INFORMATION FEATURES • Bit organization Part No. A ccess Time Package MX23L6410MC-12 120ns 44 pin SOP MX23L6410MC-15 150ns 44 pin SOP MX23L6410TC-12 120ns 48 pin TSOP 8M x 8 (byte mode)

HM62256BLP-7SL

Abstract: hm62256blfp-7t
Contextual Info: ADE-203-135C Z HM62256B Series 32,768-word x 8-bit High Speed CMOS Static RAM HITACHI The Hitachi HM62256B is a CMOS static RAM organized 32-kword x 8-bit. It realizes higher perfo rm an ce and low pow er consum ption by employing 0.8 |jm Hi-CMOS process technology.

triac tag 8518

Abstract: 70146 DS3654 X2864AD 7 segment display RL S5220 TC9160 la 4440 amplifier circuit diagram 300 watt philips ecg master replacement guide vtl 3829 A-C4 TCA965 equivalent
Contextual Info: 1985 0 / 0 / CONTENTS VOLUME I Introduction to IC MASTER 3 Advertisers’ Index 8 Master Selection Guide Function Index I0 Part Number Index 40 Part Number Guide 300 Logo Guide 346 Application Note Directory 349 Military Parts Directory 50I Testing 506 Cross Reference

Contextual Info: S O N Y 1 C X K 5 T 8 5 1 2 T M /T N 65536-word x 8-bit High Speed CMOS Static RAM -1 0 L L X /1 2 L L X Preliminary Description The CXK5T8512TM/TN is a high speed CMOS static RAM organized as 65536-words by 8-bits. Special feature are low power consumption and

Contextual Info: TMS29LF4Q0T, TMS29LF400B 524288 BY 8-BIT/262144 BY 15-BIT FLASH MEMORIES * Single Power Supply Supports 2.7-V and 3.6-V Read/Write Operation f • • • • 524288 By 8 Bits 262144 By 16 Bits Array-Blocking Architecture - One 16K-Byte/One 8K-Word Boot Sector

texas ic 6116

Contextual Info: TMS27C512 524.288-BIT ERASABLE PROGRAMMABLE READ-ONLY MEMORY TMS27PC512 524,288 BIT PROGRAMMABLE READ-ONLY MEMORY N O VEM BER 1985 - This Data Sheet is Applicable to AH TMS27C512s and TMS27PC512s Symbolized w ith Code "A " as Described on Page 12. J AND N PACKAGE