A2241
Abstract: 82C691 CY2254ASC-2 CY27C010 CY82C691 CY82C692 CY82C693 CY82C694 8kx1 RAM ma897
Text: 1CY 82C6 91 PRELIMINARY 82C691 Pentium hyperCache™ Chipset System Controller Features • Supports mixed standard page-mode and EDO DRAMs • Supports the VESA Unified Memory Architecture VUMA • Support for standard 72-bit-wide DRAM banks • Supports non-symmetrical DRAM banks
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CY82C691
72-bit-wide
208-pin
A2241
82C691
CY2254ASC-2
CY27C010
CY82C691
CY82C692
CY82C693
CY82C694
8kx1 RAM
ma897
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CY2254ASC-2
Abstract: CY27C010 CY82C691 CY82C692 CY82C693 CY82C694 82C691 cy82 processor amd k5
Text: ADVANCED INFORMATION CY82C690 Pentiumt hyperCachet Chipset DataĆPath/Integrated Cache for hC-ZX Solution Features D D D D Supports all 3.3V PentiumtĆclass processors, AMD K5, and Cyrix M1 CPUs Directly interfaces with 82C691 and CY82C693 to provide a highĆperformance threeĆchip zero
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CY82C690
CY82C691
64bit
CY82C693
CY2254ASC-2
CY27C010
CY82C691
CY82C692
CY82C694
82C691
cy82
processor amd k5
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VT82C691
Abstract: HD04 vt82c motherboard VT82C596 82c691 via apollo via vt82c VIA Apollo Master VIA Apollo Design Guide acc dram controller
Text: ZFRQQHFW H 97& $SROOR3UR 0+] 6LQJOH&KLS6RFNHW6ORW1RUWK%ULGJH IRU'HVNWRSDQG0RELOH3&6\VWHPV ZLWK$*3DQG3&, SOXV$GYDQFHG &&0HPRU\&RQWUROOHU VXSSRUWLQJ6'5$0('2DQG 3* 3UHOLPLQDU\5HYLVLRQ -XO\ 9,$7(&+12/2*,(6,1&
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492-Pin
35x35x2
MO-151
VT82C691
HD04
vt82c motherboard
VT82C596
82c691
via apollo
via vt82c
VIA Apollo Master
VIA Apollo Design Guide
acc dram controller
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8kx1 RAM
Abstract: 82C691 CY10 CY82C691 CY82C692 CY82C693 512k ADS22
Text: ADVANCED INFORMATION Features Pentiumt hyperCachet Chipset System Controller D Supports synchronous or asynchronous PCI operation D Supports six banks of DRAM six RAS lines D D D Supports DRAM densities up to 16 Mb D Provides glueless (0 TTL) system solution with CY82C692 and
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CY82C692
CY82C693
208pin
8Kx21
8kx1 RAM
82C691
CY10
CY82C691
CY82C693
512k
ADS22
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AMD k6 addressing mode
Abstract: 82C691 CY2254ASC-2 CY27C010 CY82C691 CY82C692 CY82C693 CY82C694 cy82 amd k5 32 bit block diagram
Text: fax id: 3806 1h C-DX PRELIMINARY CY82C69x Pentium hyperCache™ Chipset Family System Features — General purpose I/O pins and registers • Flexible power management with five timers and ten programmable event detectors • Full system, data, cache, and peripheral control
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CY82C69x
CY82C691
CY82C692
128-KB
CY82C693
CY82C693U
CY82C694
128-KB
8Kx21
AMD k6 addressing mode
82C691
CY2254ASC-2
CY27C010
cy82
amd k5 32 bit block diagram
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CY2254ASC-2
Abstract: CY27C010 CY82C691 CY82C692 CY82C693 CY82C694
Text: PRELIMINARY Pentium CY82C692 t hyperCachet Chipset DataĆPath/Integrated Cache for hC-VX, hC-DX Solutions Features D D Supports all 3.3V PentiumtĆclass processors, AMD K5, and Cyrix M1 CPUs Directly interfaces with 82C691 and CY82C693 to provide highĆperformance threeĆchip Pentium
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CY82C692
CY82C691
CY82C693
64bit
128KB)
CY2254ASC-2
CY27C010
CY82C691
CY82C692
CY82C694
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CY82C691
Abstract: CY82C691-NC 110C 130C 140C 95441
Text: Qualification Report September 1996, QTP# 95431, Version 1.0 PentiumTM hyperCacheTM Chipset System Controller 82C691, 208-Pin Plastic Quad Flatpack Pentium is a trademark of Intel Corporation hyperCache is a trademark of Cypress Semiconductor Corporation
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CY82C691,
208-Pin
CY82691
208-Pins
CY82C691-NC
CY82C691
CY82C691-NC
110C
130C
140C
95441
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MD34
Abstract: CNTL10 82C691 CY2254ASC-2 CY27C010 CY82C691 CY82C692 CY82C693 CY82C694 CNTL6
Text: 1CY 82C6 92 CY82 C6 92 PRELIMINARY CY82C692 Pentium hyperCache™ Chipset Data-Path Controller with Integrated Cache Features • On-Chip 8-Deep FIFOs support Post-Writing/Pre-Reading PCI data • Provides Data steering and Bus size conversion • 16K by 64 128-KB Integrated Pipelined BSRAM
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CY82C692
128-KB)
208-pin
MD34
CNTL10
82C691
CY2254ASC-2
CY27C010
CY82C691
CY82C692
CY82C693
CY82C694
CNTL6
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82C691
Abstract: CY2254ASC-2 CY27C010 CY82C691 CY82C692 CY82C694 cy82 C691H
Text: PRELIMINARY 82C691 Pentiumt hyperCachet Chipset System Controller Features DProvides power management support DSupports six banks of DRAM six RAS DIntegrated 8Kx21 tag (direct mapped or DSupports DRAM densities up to 16 Mb DUp to 768 MB main memory Dvariable drive on DRAM address and
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CY82C691
8Kx21
82C691
CY2254ASC-2
CY27C010
CY82C691
CY82C692
CY82C694
cy82
C691H
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2561b
Abstract: CPU 314 IFM 8kx1 RAM cy17 ALI chipset fast page mode dram controller CY2254ASC-2 CY27C010 CY82C691 CY82C693
Text: PRELIM INARY 82C691 Pentium hyperCache™ Chipset System Controller Features Supports mixed standard page-mode and EDO DRAMs Supports the VESA Unified Memory Architecture VUMA Support for standard 72-bit-wide DRAM banks Supports non-symmetrical DRAM banks
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CY82C691
8Kx21
2561b
CPU 314 IFM
8kx1 RAM
cy17
ALI chipset
fast page mode dram controller
CY2254ASC-2
CY27C010
CY82C691
CY82C693
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1MD45
Abstract: cy17 High-Zt11-12 CY10 CY82C691 CY82C692 CY82C693 DQ23P cy82
Text: PRELIM INARY CY82C692 W CYPRESS Pentium hyperCache™ Chipset Data-Path Controller with Integrated Cache Features • Supports ail 3.3V Pentium™-class processors, AMD K5, K6 and Cyrix M1 CPUs • Two-bit wraparound counter supporting Intel Burst or Linear burst sequence
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CY82C692
CY82C691
CY82C693
64-bit
128-KB)
55fiTbbE
1MD45
cy17
High-Zt11-12
CY10
CY82C692
DQ23P
cy82
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Untitled
Abstract: No abstract text available
Text: PRELIMINARY CY82C692 Pentium hyperCache™ Chipset Data-Path/Integrated Cache for h C -VX, h C -D X Solutions Features Two-bit wraparound counter supporting Intel Burst or Linear burst sequence Supports 3-1-1-1 Level 2 cache operation up to 66 MHz bus speed
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CY82C692
CY82C691
CY82C693
64-bit
128-KB)
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692CU
Abstract: 82c pci isa
Text: PRELIMINARY CY82C692 Pentium hyperCache™ Chipset Data-Path Controller with Integrated Cache Features • O n -C h ip 8-D ee p F IF O s s u p p o rt P o st-W ritin g /P re-R e ad ing PCI data • S u p p o rts all 3.3 V P e n tiu m ™ -c la s s p ro ces so rs , A M D
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CY82C692
CY82C
CY82C691
692CU
82c pci isa
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8kx1 RAM
Abstract: 82c pci isa tagram
Text: Pentium hyperCache™ Chipset System Controller Featu res Supports mixed standard page-mode and EDO DRAMs Supports the VESA Unified Memory Architecture VUMA Support fo r standard 72-bit-wide DRAM banks • Provides control fo rth e cache, system memory, and the
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8Kx21
72-bit-wide
8kx1 RAM
82c pci isa
tagram
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VT82C586B motherboard
Abstract: HD60 PULSE GENERATOR slot AGP pinout
Text: ’M WATechimtogies,:, W if fli 82C691 ßom eei VIA 82C691 A pollo P ro 66 / 100 MHz Single-Chip Socket-8 / Slot-1 North Bridge for Desktop and Mobile PC Systems with AGP and PCI plus Advanced ECC Memory Controller supporting SDRAM, EDO, and FPG • AGP / PCI / ISA Mobile and Deep Green PC Ready
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VT82C691
VT82C586B
208-pin
VT82C596
324-contact
492-Pin
VT82C586B motherboard
HD60 PULSE GENERATOR
slot AGP pinout
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Untitled
Abstract: No abstract text available
Text: PRELIM INARY CY82C692 Pentium hyperCache™ Chipset Data-Path Controller with Integrated Cache Features • Supports ail 3.3V Pentium™-class processors, AMD K5, K6 and Cyrix M1 CPUs • Two-bit wraparound counter supporting Intel Burst or Linear burst sequence
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OCR Scan
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PDF
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CY82C692
CY82C691
CY82C693
64-bit
CY82C691
128-KB)
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Untitled
Abstract: No abstract text available
Text: PRELIM INARY 82C691 Pentium hyperCache™ Chipset System Controller Features • Provides control for the cache, system memory, and the PCI bus • PCI Bus Rev. 2.1 compliant • Supports 3V Pentium™, AMD K5, K6, and Cyrix 6x86 M1 CPUs • Support for WB or WT L1 cache
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CY82C691
8Kx21
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CY10
Abstract: CY2254ASC-2 CY27C010 CY82C691 CY82C692 CY82C693 QCPL
Text: : rr^n r- r* r* O i l PRELIMINARY C Y82C692 i ll L o D = Pentium hyperCache™ Chipset Data-Path/Integrated Cache for hC-VX, hC-DX Solutions Features • Supports all 3.3V Pentium™ -class processors, AMD K5, and Cyrix M1 CPUs • Directly interfaces with 82C691 and CY82C693 to
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CY82C692
CY82C691
CY82C693
64-bit
128-KB)
CY10
CY2254ASC-2
CY27C010
CY82C692
QCPL
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M/CY10
Abstract: No abstract text available
Text: L>il Hilbh iT ^ irT^n r n n rssgggppr PRELIMINARY - CY82C690 Pentium hyperC ache™ C hipset Data-Path/lntegrated Cache for hC-ZX Solution Features • Supports all 3.3V Pentium™ -class processors, AMD K5, and Cyrix M1 CPUs • Directly interfaces with 82C691 and CY82C693 to
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CY82C690
CY82C691
CY82C693
64-bit
64-KB)
M/CY10
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CYL7
Abstract: Cyrix 6x86 MX CPU 82c691
Text: PRELIMINARY 82C691 Pentium hyperCache™ Chipset System Controller •Provides power management support through SMM APM Compliant •Integrated 8Kx21 tag (direct mapped or two-way set associative) •Support for cache sizes up to 1 MB •Supports mixed standard page-mode
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OCR Scan
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CY82C691
8Kx21
72-bit-wide
CYL7
Cyrix 6x86 MX CPU
82c691
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Untitled
Abstract: No abstract text available
Text: L>il Hilbh iT ^ irT^n r n n rssgggppr PRELIMINARY - CY82C692 Pentium hyperCache™ Chipset Data-Path/lntegrated Cache for hC-VX, hC-DX Solutions Features • Supports all 3.3V Pentium™ -class processors, AMD K5, and Cyrix M1 CPUs • Directly interfaces with 82C691 and CY82C693 to
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OCR Scan
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PDF
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CY82C691
CY82C693
64-bit
128-KB)
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Untitled
Abstract: No abstract text available
Text: ADVANCED INFORMATION CY82C690 Pentium hyperCache™ Chipset Data-Path/Integrated Cache for h C -Z X Solution Features Two-bit wraparound counter supporting Intel Burst or Linear burst sequence Supports 3-1-1-1 Level 2 cache operation up to 66 MHz bus speed
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OCR Scan
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PDF
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CY82C690
33YPentiumTM
CY82C691
CY82C693
64-bit
32-KB)
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