74F11 Search Results

Contextual Info: ADVANCE INFORMATION SN 54F114, SN 74F114 DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH PRESET. COM MON CLEAR, AND COMMON CLOCK D2932, MARCH 1987 Package Options Include Plastic "Small Outline" Packages, Ceramic Chip Carriers, and Standard Plastic and Ceramic 300-mil

Contextual Info: S E M IC O N D U C T O R tm 74F113 Dual JK Negative Edge-Triggered Flip-Flop Asynchronous input: G en eral D escrip tio n The ’F113 offers individual J, K, Set and Clock inputs. When the clock goes HIGH the inputs are enabled and data may be entered. The logic level of the J and K inputs may be

Contextual Info: General Description This device contains three independent gates, each of which performs the logic AND function. Ordering Code: Commercial Military Package Number 74F11PC N14A 54F11DM Note 2 J14A te See Section 0 Package Description 14-Lead (0.300" Wide) Molded Dual-In-Line

KL SN 102

Abstract: 74F113 74F113PC 74F113SC 74F113SJ M14A M14D MS-001 N14A
Contextual Info: Revised July 1999 E M IC D N D U C T D R T M 74F113 Dual JK Negative Edge-Triggered Flip-Flop transferred to the outputs on the falling edge of the clock pulse. General Description T he 74F113 offers individual J, K, Set and C lo ck inputs. W hen the clock goes H IGH the inputs are enabled and

Contextual Info: @ M OTOROLA Advance Information M C 5 4 F 1 1 4 M C 7 4 F 1 1 4 DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP WITH COMMON CLOCKS AND CLEARS DESCRIPTION— MC54F/74F114 co nta in s tw o high-speed JK flip flo p s w ith co m m o n clock and Clear inputs. S yn ch ro n o us state

Contextual Info: Ä M O T O R O L A MC54F/74F112 P r o d u c t P r e v ie w DUAL JK NEGATIVE EDGE-TRIGGERED FUP-FLOP DESCRIPTION — MC54F/74F112 contains two independent, high­ speed JK flip-ftops with Direct Set and Clear inputs. Synchronous state changes are initiated by the falling edge of the clock. Trig­

74F113

Abstract: 74F113PC 74F113SC 74F113SJ M14A M14D MS-001 N14A
Contextual Info: Revised July 1999 74F113 Dual JK Negative Edge-Triggered Flip-Flop General Description The 74F113 offers individual J, K, Set and Clock inputs. When the clock goes HIGH the inputs are enabled and data may be entered. The logic level of the J and K inputs may be changed when the clock pulse is HIGH and the flipflop will perform according to the Truth Table as long as

jk flip flop

Abstract: 74F114 74F114PC 74F114SC C1995 F114 M14A N14A
Contextual Info: 74F114 Dual JK Negative Edge-Triggered Flip-Flop with Common Clocks and Clears General Description The ’F114 contains two high-speed JK flip-flops with common Clock and Clear inputs Synchronous state changes are initiated by the falling edge of the clock Triggering occurs at a voltage level of the clock and is not directly related

Contextual Info: S E M IC O N D U C T O R tm 74F113 Dual JK Negative Edge-Triggered Flip-Flop General Description Asynchronous input: The ’F113 offers individual J, K, Set and Clock inputs. When the clock goes HIGH the inputs are enabled and data may be entered. The logic level of the J and K inputs may be

Contextual Info: rnm ps oem iconaucior*-digneucs r A d i rro a u cis rro a u c i specmcauon Dual J - K negative edge-triggered flip-flops without reset 74F113 FEATURE TYPE TYPICAL fm, TYPICAL SUPPLY CURRENT* TOTAL • Industrial temperature range available -40°C to +85°C)

Contextual Info: 54F11,74F11 Triple 3-Input AND Gate Literature Number: SNOS150A General Description This device contains three independent gates, each of which performs the logic AND function. Ordering Code: Commercial Military Package Number 74F11PC N14A 54F11DM Note 2

Contextual Info: E M IC O N D U C T O R T 74F114 Dual JK Negative Edge-Triggered Flip-Flop with Common Clocks and Clears General Description A synchronous Inputs: The ’F114 contains tw o high-speed JK flip-flops with com ­ mon C lock and C lear inputs. Synchronous state changes are

74F112

Contextual Info: E M I R ¡ C O C H April 1988 I L D N D U C T O Revised July 1999 R TM 74F112 Dual JK Negative Edge-Triggered Flip-Flop General Description Simultaneous LOW signals on S q and C q force both Q and The 74F112 contains two independent, high-speed JK flipflops with Direct Set and Clear inputs. Synchronous state

Contextual Info: Revised Ju ly 1999 S E M IC O N D U C T O R TM 74F11 Triple 3-Input AND Gate General Description This device contains three independent gates, each of w hich perform s the logic AND function. Ordering Code: Order Number Package Number Package Description 74F11SC

74F11

Abstract: 54F11DM 54F11FM 54F11LM 74F11PC 74F11SC 74F11SJ J14A M14A N14A
Contextual Info: 54F 74F11 Triple 3-Input AND Gate General Description This device contains three independent gates each of which performs the logic AND function Commercial Package Number Military 74F11PC Package Description N14A 14-Lead 0 300 Wide Molded Dual-In-Line J14A

Contextual Info: 114 54F/74F114 Connection Diagrams Dual JK Negative Edge-Triggered Flip-Flop With Common Clocks and Clears Ki [ 7 i7 ] v c c 5 ~ r ~ L L Kt CP Jt 1 3] CP ' >- O C D S d i 0 Qi Qi H ] K2 • ji [7 Description s d i The 'F114 contains two high-speed JK flip-flops with common Clock and

Contextual Info: 11 54F/74F11 Triple 3-Input AND Gate Connection Diagrams Pin Assignment for DIP and SOIC Pin Assignment for LCC and PCC Ordering Code: See Section 5 Input Loading/Fan-Out: See Section 3 for U.L. definitions 54F/74F U.L. HIGH/LOW Description Pin Names Inputs

74F10

Abstract: 74F11 n74f10 N74F10D N74F10N N74F11D N74F11N
Contextual Info: Philips Semiconductors-SigneHcs Document No. 853-0329 ECN No. 97683 Date o f issue September 2 0 ,1 98 9 Status Product Specification FAST 74F10, 74F11 Gates 74F10 Triple 3-Input NAND Gate 74F11 Triple 3-Input AND Gate FAST Products TYPE TYPICAL PROPAGATION

E 94733

Abstract: E 94733 3 74F113 74F113PC 74F113SC 74F113SJ C1995 F113 M14A M14D
Contextual Info: 74F113 Dual JK Negative Edge-Triggered Flip-Flop General Description The ’F113 offers individual J K Set and Clock inputs When the clock goes HIGH the inputs are enabled and data may be entered The logic level of the J and K inputs may be changed when the clock pulse is HIGH and the flip-flop will

Contextual Info: 112 54F/74F112 Connection Diagrams Dual J K Negative Edge-Triggered Flip-Flop CP- [7 Description The 'F112 contains two independent, high-speed J K flip-flops with Direct Set and Clear inputs. Synchronous state changes are initiated by the falling edge of the clock. Triggering occurs at a voltage level of the clock

74F112

Abstract: 74F112PC 74F112SC 74F112SJ M16A M16D MS-001 N16E h0023
Contextual Info: Revised July 1999 E M IC D N D U C T D R T M 74F112 Dual JK Negative Edge-Triggered Flip-Flop General Description S im ultaneous LOW signals on S q and C q force both Q and T he 74F112 contains tw o independent, high-speed JK flip­ flops w ith D irect Set and C lear inputs. Synchronous state

Contextual Info: Philips Semiconductors Product specification Dual J-K negative edge-triggered flip-flops without reset FEATURE 74F113 PIN CONFIGURATION • Industrial temperature range available –40°C to +85°C CP0 1 14 VCC K0 2 13 CP1 DESCRIPTION The 74F113, dual negative edge-triggered JK-type flip-flop, features

SF00106

Abstract: SF00103
Contextual Info: Philips Semiconductors Product specification Dual J-K negative edge-triggered flip-flop FEATURE 74F112 PIN CONFIGURATION • Industrial temperature range available –40°C to +85°C CP0 1 16 VCC DESCRIPTION K0 2 15 RD0 The 74F112, Dual Negative Edge-Triggered JK-Type Flip-Flop,

schmitt trigger non inverting

Abstract: 74F864 3 bit magnitude comparator 74F154 74F579 74F5300 equivalent multiplexer 30 pin QUAD D FLIP-FLOP "FAST TTL" 74*545
Contextual Info: Philips Semiconductors Section 2 FAST TTL Logic Devices FAST TTL Logic Series CONTENTS 74F00 74F02 74F04 74F06 74F06A 74F07 74F07A 74F08 74F10 74F11 74F14 74F20 74F27 74F30 74F32 74F37 74F38 74F51 74F64 74F74 74F85 74F86 74F109 74F112 74F113 74F125 74F126