512KBITS Search Results

80C167

Abstract: 80C196 80C186 80C31 MC68HC16 PSD4256G6V TQFP80 psd4xx 80c196 instruction 68HC11 EVENT COUNTER
Contextual Info: PSD4256G6V Flash In-System Programmable ISP Peripherals for 8-bit or 16-bit MCUs PRELIMINARY DATA FEATURES SUMMARY • DUAL BANK FLASH MEMORIES Figure 1. Package – 8Mbits of Primary Flash Memory (16 uniform sectors, 64Kbyte) – 512Kbits of Secondary Flash Memory with 4

W39L512P-90

Abstract: W39L512P-70
Contextual Info: Preliminary W39L512 64K x 8 CMOS FLASH MEMORY 1. GENERAL DESCRIPTION The W39L512 is a 512Kbit, 3.3-volt only CMOS flash memory organized as 64K × 8 bits. For flexible erase capability, the 512Kbits of data are divided into 16 small even pages with 4 Kbytes. The bytewide × 8 data appears on DQ7 − DQ0. The device can be programmed and erased in-system with a

W39L512

Contextual Info: W39L512 64K x 8 CMOS FLASH MEMORY 1. GENERAL DESCRIPTION The W39L512 is a 512Kbit, 3.3-volt only CMOS flash memory organized as 64K × 8 bits. For flexible erase capability, the 512Kbits of data are divided into 16 small even pages with 4 Kbytes. The bytewide × 8 data appears on DQ7 − DQ0. The device can be programmed and erased in-system with a

Contextual Info: W39L512 64K x 8 CMOS FLASH MEMORY 1. GENERAL DESCRIPTION The W39L512 is a 512Kbit, 3.3-volt only CMOS flash memory organized as 64K × 8 bits. For flexible erase capability, the 512Kbits of data are divided into 16 small even pages with 4 Kbytes. The bytewide × 8 data appears on DQ7 − DQ0. The device can be programmed and erased in-system with a

Contextual Info: TL16C552 DUAL ASYCHRONOUS COMMUNICATIONS ELEMENT WITH FIFO _ SLLS102B - DECEMBER 1990 - REVISED MARCH 1996 • IBM PC/AT Compatible • Programmable Serial Interface Characteristics for Each Channel: - 5-, 6-, 7-, or 8-bit Characters

f71882fg

Abstract: fintek f71882fg f71882 AUTOMATIC 12V PC FAN CONTROL BY USING THERMISTOR scr speed control dc motor PC intel ICH8 MOTHERBOARD FAN MOTOR CONTROL SPEED WITH LM358 micro USB Connector AB type Female dual stacked FINTEK F71882FG IO FAN MOTOR CONTROL SPEED WITH LM358 PWM
Contextual Info: F71882 F71882 Super Hardware Monitor + LPC I/O Release Date: May, 2008 Version: V0.28P May, 2008 V0.28P F71882 F71882 Datasheet Revision History Version 0.20P 0.21P Date 2005/10/14 2005/12/08 Page 8 13 50 53 103 105 106 107 0.21P 0.22P 2005/12/14 2005/12/19

Contextual Info: TMS320C6712, TMS320C6712C FLOATINGĆPOINT DIGITAL SIGNAL PROCESSORS SPRS148D – AUGUST 2000 – REVISED MARCH 2003 D Best Price/Performance Digital Signal D D D D D Processors DSPs : TMS320C67x (TMS320C6712, TMS320C6712C) – Eight 32-Bit Instructions/Cycle

common mode rejection ratio test 1553B

Abstract: rta2 1553 SUmmit
Contextual Info: 1.0 INTRODUCTION The monolithic SµMMIT provides the system designer with an intelligent solution to MIL-STD-1553 multiplexed serial data bus design problems. The SµMMIT is a single-chip device that implements all three of the defined MIL-STD-1553 functions Remote Terminal, Bus Controller, and Monitor. Operating either

features and architecture of tms320c6x

Abstract: C6201 TMS320C6201 TMS320C6202 TMS320C6X velocITI velocITI of tms320c6x TMS320C6X FEATURES features architecture applications TMS320C6x TMs320C542
Contextual Info: EXTENDING YOUR REACHTM NORTH AMERICAN EDITION INTEGRATION AN UPDATE ON TEXAS INSTRUMENTS SEMICONDUCTORS VOL. 14 ▼ NO. 1 ▼ FEBRUARY 1997 The TMS320C6201 pushes the en- TI’S TMS320C6X velope with the most advanced features to PUSHES THE ENVELOPE .in DSP performance, time-to-market,

ADSP-21065L

Abstract: EE-66 EE-69 0x20010
Contextual Info: Engineer to Engineer Note EE-58 Technical Notes on using Analog Devices’ DSP components and development tools from the DSP Division Phone: 800 ANALOG-D, FAX: (781) 461-3010, FTP: ftp.analog.com, EMAIL: dsp.support@analog.com Executing Code from External

Contextual Info: ASAHI KASEl AK2312 Preliminary = - 4.8kbps SPEECH CODEC LSI Over View AK2312 is a low cost CELP based 4.8 kbps speech CODEC LSI. As it has a memory interface for three types of memories DRAM, SRAM, ROM and two set sof serial I/O interface, it can be easily applied to telephone answering machine

Contextual Info: F eatures □ Comprehensive M IL-STD-1553 dual redundant Bus Controller BC , Remote Terminal (RT), and Monitor Terminal (MT) with integrated Bus Transceivers, Memory, and Memory Management Unit (MMU) □ Compliant MIL-STD-1553B, Notice II RT - Internal command ¡¡legalization in the RT mode

Contextual Info: 1.0 I n t r o d u c t io n 1.1.3 Circular Buffers The monolithic SUMMIT provides the system designer with an intelligent solution to MIL-STD-1553 multiplexed serial data bus design problems. The SUMMIT is a single-chip device that implements all three of the defined MIL-STD-1553 functions Remote Terminal, Bus Controller, and Monitor. Operating

Contextual Info: RTL8305SB -Ver. D SINGLE-CHIP 5-PORT 10/100MBPS SWITCH CONTROLLER WITH DUAL MII INTERFACES DATASHEET Rev. 1.2 10 June 2003 Track ID: JATR-1076-21 RTL8305SB-Ver. D Datasheet COPYRIGHT 2003 Realtek Semiconductor Corp. All rights reserved. No part of this document may be reproduced, transmitted,

C2553

Abstract: nc 1458 p1 Sunny Oscillators MSM9802 MSM9803 MSM9805 SSOP30-P-56-0 MSC1157 kyocera cr resistor
Contextual Info: Dear customers, About the change in the name such as "Oki Electric Industry Co. Ltd." and "OKI" in documents to OKI Semiconductor Co., Ltd. The semiconductor business of Oki Electric Industry Co., Ltd. was succeeded to OKI Semiconductor Co., Ltd. on October 1, 2008.

F71882

Abstract: FAN MOTOR CONTROL SPEED WITH LM358 PWM FAN MOTOR CONTROL SPEED WITH LM358 dc motor speed control lm358 fintek io controller h55 MOTHERBOARD CIRCUIT diagram f71883fg f71883f lm358 fan control DC MOTOR 3600RPM
Contextual Info: F71883 F71883 Super Hardware Monitor + LPC I/O Release Date: July, 2009 Version: V0.28P July, 2009 V0.28P F71883 F71883 Datasheet Revision History Version Date Page Revision History 0.20P 2005/10/14 - Release Version 0.21P 2006/01/20 - Added new functions Intel PECI/SST interface and

Contextual Info: GT24C512 GT24C512 2-WIRE 512K Bits Serial EEPROM Copyright 2013 Giantec Semiconductor Inc. Giantec . All rights reserved. Giantec reserves the right to make changes to this specification and its products at any time without notice. Giantec products are not designed, intended, authorized or warranted for use as components in systems or equipment intended for critical medical or surgical equipment,

Digital ECHO microphone mixing circuit

Abstract: analog ECHO microphone mixing circuit 7-band graphic equalizer voice changer circuits diagram voice changer mic music auto level control Karaoke Processor IC voice changer microphone 2 parts Trimmer POT 1M Simple Digital ECHO microphone mixing circuit
Contextual Info: I p NJU25102 r Digital Karaoke Audio Processor ^ Description Features The NJU25102 is a dedicated audio processor IC which supports all of the popular functions needed to implement a high performance Karaoke sound system. The NJU25102 ¡s a complete DSP-based system,

Contextual Info: M25P64 64 Mbit, Low Voltage, Serial Flash Memory With 50MHz SPI Bus Interface FEATURES SUMMARY • ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ 64Mbit of Flash Memory 2.7 to 3.6V Single Supply Voltage SPI Bus Compatible Serial Interface 50MHz Clock Rate maximum

Contextual Info: HY5V16CF 2 Banks x 512K x 16Bit Synchronous DRAM DESCRIPTION The Hynix HY5V16CF is a 16,777,216-bit CMOS Synchronous DRAM, ideally suited for the main memory applications which require large memory density and high bandwidth. HY5V16CF is organized as 2banks of 524,288x16.

HY57V161610D

Abstract: HY57V161610DTC-10I HY57V161610DTC-55I HY57V161610DTC-6I HY57V161610DTC-7I
Contextual Info: HY57V161610D 2 B a n k s x 5 1 2 K x 1 6 B it S y n c h r o n o u s D R A M DESCRIPTION THE Hynix HY57V161610D is a 16,777,216-bits CMOS Synchronous DRAM, ideally suited for the Mobile applications which require low power consumption and industrial temperature range. HY57V161610D is organized as 2banks of

Contextual Info: SEPTEMBER 1994 ADVANCE INFORMATION DS3511 - 2.2 VP2612 VIDEO MULTIPLEXER Supersedes version in December 1993 Digital Video & DSP IC Handbook, HB3923-1 FEATURES • Fully integrated H261 video multiplexer ■ Inputs data direct from VP2611 source coder ■

HY57V161610E

Abstract: HY57V161610ET-10I HY57V161610ET-15I HY57V161610ET-55I HY57V161610ET-5I HY57V161610ET-6I HY57V161610ET-7I HY57V161610ET-8I HY57V161610ET-I
Contextual Info: HY57V161610ET-I 2 Banks x 512K x 16 Bit Synchronous DRAM DESCRIPTION THE Hynix HY57V161610E is a 16,777,216-bits CMOS Synchronous DRAM, ideally suited for the main memory and graphic applications which require large memory density and high bandwidth. HY57V161610E is organized as 2banks of 524,288x16.

Contextual Info: KM68V512A, KM68U512A Family CMOS SRAM 64Kx8 bit Low Power & Low Vcc CMOS Static RAM FEATURE SUMMARY GENERAL DESCRIPTION • Process Technology : 0.6 um CMOS • Organization : 64K x 8 • Power Supply Voltage KM68V512A family : 3.3V +/- 0.3V KM68U512A family : 3.0V +/- 0.3V