480PS Search Results

Contextual Info: SONY C OR P/ COMP ONENT PROPS 5DE 03fl23fl3 D Q uint Line Receiver w ith D iffe re n tia l I/O Description Features Tpd=480ps T tlh = 2 7 0 ps T t h i= 2 2 0 ps • Internal pull down resistors on input pins to main­ tain logic LOW level with the pins left open

Contextual Info: sony . CXB1503Q-Y Quint Line Receiver with Differential I/O Description Pin Assignm ent The CXB1503Q-Y is an ultra high speed monolithic ECL IC, which contains five differential line receivers with a built-in reference voltage supply V b b . With V b b tied to one of the input pins of each differential

LVDS register

Contextual Info: CDCE72010 SCAS858C – JUNE 2008 – REVISED JANUARY 2012 www.ti.com Ten Output High Performance Clock Synchronizer, Jitter Cleaner, and Clock Distributor Check for Samples: CDCE72010 FEATURES 1 • • • • • • • • • • • • • • High Performance LVPECL, LVDS, LVCMOS

tl741

Abstract: VEL-4P32-RH-TP sodium vapor lamp Magnetek ballast F32T8 transistor ballast 1000W VEL-3P32-RH-TP 13w cfl circuit D835 transistor PHILIPS T8 MAGNETIC BALLAST
Contextual Info: Manufacturers’ Cross Reference Guide These tables are intended only as guides and may represent another lamp/ballast company's most similar product rather than an identical match. Individual manufacturer's performance values should be consulted. For a complete cross reference guide please consult our electronic

SY89540UMY

Abstract: SY89540U SY89540UMYTR SY89540UMI SY89540UMITR
Contextual Info: SY89540U Precision Low Jitter 4x4 LVDS Crosspoint Switch with Internal Termination General Description The SY89540U is a low-jitter, low skew, high-speed 4x4 crosspoint switch optimized for precision telecom and enterprise server/storage distribution applications. The SY89540U guarantees data-rates

PMB4220

Abstract: pmb4420 PMB 4420 Siemens pmb 4420 transistor smd marking gk 5-PIN MARKING PAX PMB4819 smd diode marking KC L50Q 4819
Contextual Info: tM I fl s ?l s s if 3 No. SI IC PMB4819 CODE NO. ^ 7| fl- S s| g Siemens LTD. Seoul 726,Yeoksam-dong,Kangnam-gu Seoul.C.P.O Box 3001,Korea Tel: 5277-700 Fax: 5277-779 SIEMENS ICs for Communications Power Amplifier for DECT Application PMB 4819 Version 1.0

SY89540U

Abstract: SY89540UMG SY89540UMGTR SY89540UMI SY89540UMITR
Contextual Info: SY89540U Precision Low Jitter 4x4 LVDS Crosspoint Switch with Internal Termination General Description The SY89540U is a low-jitter, low skew, high-speed 4x4 crosspoint switch optimized for precision telecom and enterprise server/storage distribution applications. The SY89540U guarantees data-rates

TS-1000-OAM

Abstract: MIC79110 TS-1000 digital ts receiver MIC2295 MIC2590B MIC2591B KS8993F micrel tx battery 3v
Contextual Info: Q3 2004 VOLUME 16 Introducing The Industry's Best-in-Class Dual-Slot Power Controllers PCI Express MIC2591B/MIC2592B PCI v2.x and PCI-X 1.0b/2.0 MIC2590B/MIC2593 Micrel's MIC259x family of multi-rail, dual-slot hot-swap controllers lowers overall system cost for implementing power controllers in PC board

tf2d

Contextual Info: Supertex inc. MD3872 Low Power, Low Noise Ultrasound Receive Front-End Eight-Channels of LNA, VGA, AAF, CPS & 12-Bit, 50MHz ADCs Features ►► ►► ►► ►► ►► ►► ►► ►► ►► ►► ►► ►► ►► ►► ►► ►► ►►

Contextual Info: CY2DM1502 1:2 CML / LVPECL Input to CML Output Fanout Buffer Features Functional Description • One current mode logic CML or low-voltage positive emitter-coupled logic (LVPECL) input pair distributed to two CML output pairs ■ 20-ps maximum output-to-output skew

ALI chipset

Abstract: KM266 SIS 650 Via KM266 48MHZ M1671 PLL202-151 ali m1671 KM26
Contextual Info: PRELIMINARY PLL202-151 Programmable Clock Generator for VIA, ALI and SIS DDR SYSTEM FEATURES • • • • • • • • • • • • • Supports VIA P4M/KM266, ALI M1671 and SIS 645/650 Chipsets. Programmable Spread Spectrum Modulation from ±0.1% to ±1.5% with minim u m step size of

1.5 V LED

Abstract: DNR120LS DNR120AS DNR120PS ok ps 210-370 230 volt ac overvoltage protection DNR120-480
Contextual Info: AC-DC 120-480 Watts xppower.com DNR120-480 Series • Up to 90% Efficiency • Wide Adjustment Range • Three-Phase 480 W Versions • Parallel Function • DC Standby Versions • Full Power to +60 ˚C • Connector Options Specification Input General Input Voltage

Contextual Info: THC63LVD1027_Rev.2.0_E THC63LVD1027 85MHz 10Bits Dual LVDS Repeater General Description Features The THC63LVD1027 LVDS Low Voltage Differential Signaling repeater is designed to support pixel data transmission between Host and Flat Panel Display up to WUXGA resolution.

Contextual Info: CY2DL1504 1:4 Differential LVDS Fanout Buffer with Selectable Clock Input Features Functional Description • Select one of two differential LVPECL, LVDS, HCSL, or CML input pairs to distribute to four LVDS output pairs ■ 30-ps maximum output-to-output skew

ph5ad

Abstract: REG0011 LVPECL PH6AD
Contextual Info: CDCE72010 www.ti.com. SCAS858 – JUNE 2008 Ten Output High Performance Clock Synchronizer, Jitter Cleaner, and Clock Distributor

Contextual Info: 2 X 2 PROTECTION CROSSPOINT SWITCH DESCRIPTION FEATURES • ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ SuperLite SY55854U Guaranteed fMAX >2.5GHz over temperature 2.3V to 5.7V power supply Non-blocking “switch architecture” Guaranteed <15ps channel-to-channel skew

Contextual Info: SY89540U Precision Low Jitter 4x4 LVDS Crosspoint Switch with Internal Termination General Description The SY89540U is a low-jitter, low skew, high-speed 4x4 crosspoint switch optimized for precision telecom and enterprise server/storage distribution applications. The SY89540U guarantees data-rates

7301B

Abstract: 162MHz 7301A CH7009B
Contextual Info: CH7009/CH7301 Chrontel CHRONTEL CHRONTEL CHRONTEL Technical Bulletin 41 DVI OUTPUT EYE DIAGRAMS OF CH7009A/7301A VS. CH7009B/7301B Scope CH7009B/7301B, which are the successors of CH7009A/7301A, are fully DDWG compliant DVI transmitters. The new chips are able to transmit DVI display data from 25MHz up to 165 MHz pixel clocks. CH7009A/7301A

Contextual Info: THC63LVD1027_Rev.3.00_E THC63LVD1027 Dual Link LVDS Repeater General Description Features The THC63LVD1027 LVDS Low Voltage Differential Signaling repeater is designed to support pixel data transmission between Host and Flat Panel Display up to WUXGA resolution.

Contextual Info: THC63LVD1027_Rev.2.0_E THC63LVD1027 85MHz 10Bits Dual LVDS Repeater General Description Features The THC63LVD1027 LVDS Low Voltage Differential Signaling repeater is designed to support pixel data transmission between Host and Flat Panel Display up to WUXGA resolution.

RGC S-PQFP-N64

Abstract: ph5ad CMOS divider 10 100 1000 CDCE72010 QFN-64 LE 9540
Contextual Info: CDCE72010 www.ti.com. SCAS858 – JUNE 2008 Ten Output High Performance Clock Synchronizer, Jitter Cleaner, and Clock Distributor

frequency detection using FPGA

Contextual Info: LatticeSC PURESPEED I/O Adaptive Input Logic User’s Guide April 2008 Technical Note TN1158 Introduction Today’s high speed synchronous interfaces pose challenges to the designer in maintaining clock-to-data relationships, managing data-to-data skew, and sustaining jitter tolerance. Many next-generation interconnects use SERDES based interfaces where the clock is embedded inside the data signal. SERDES-based interfaces, however,

Contextual Info: Supertex inc. MD3872 Low Power, Low Noise Ultrasound Receive Front-End Eight-Channels of LNA, VGA, AAF, CPS & 12-Bit, 50MHz ADCs Features ►► ►► ►► ►► ►► ►► ►► ►► ►► ►► ►► ►► ►► ►► ►► ►► ►►

2DL15

Abstract: 2DL-15 2VBQ
Contextual Info: CY2DL1504 1:4 Differential LVDS Fanout Buffer with Selectable Clock Input Features Functional Description • Select one of two differential LVPECL, LVDS, or CML input pairs to distribute to four LVDS output pairs ■ 30-ps maximum output-to-output skew